diff --git a/arch/arm/configs/vmx51_defconfig b/arch/arm/configs/vmx51_defconfig index e69de29..433eaaa 100644 --- a/arch/arm/configs/vmx51_defconfig +++ b/arch/arm/configs/vmx51_defconfig @@ -0,0 +1,2208 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Thu Oct 27 13:34:41 2011 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_BZIP2 is not set +CONFIG_KERNEL_LZMA=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +# CONFIG_TREE_RCU is not set +# CONFIG_TREE_PREEMPT_RCU is not set +CONFIG_TINY_RCU=y +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +# CONFIG_SLUB is not set +CONFIG_SLOB=y +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX37 is not set +# CONFIG_ARCH_MXC91231 is not set +CONFIG_ARCH_MX5=y +CONFIG_MXC_SDMA_API=y +CONFIG_SDMA_IRAM=y +CONFIG_SOC_IMX51=y +CONFIG_ARCH_MX51=y +CONFIG_FORCE_MAX_ZONEORDER=13 +# CONFIG_MACH_MX51_3DS is not set +# CONFIG_MACH_MX51_BABBAGE is not set +CONFIG_MACH_VMX51=y +# CONFIG_MACH_MX53_EVK is not set +# CONFIG_MACH_MX53_ARD is not set +# CONFIG_MACH_MX53_SMD is not set +# CONFIG_MACH_MX53_LOCO is not set +# CONFIG_MACH_MX50_ARM2 is not set +# CONFIG_MACH_MX50_RDP is not set + +# +# MX5x Options: +# +CONFIG_ARCH_MXC_HAS_NFC_V3=y +CONFIG_ARCH_MXC_HAS_NFC_V3_2=y +CONFIG_VMX_SPIMODULE=y +CONFIG_VMX_I2CMODULE=y +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=64 +CONFIG_ISP1504_MXC=y +CONFIG_UTMI_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_TZIC=y +CONFIG_MXC_PWM=y +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_MXC_DVFS_PER=y + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_ARM_ENABLE_L2=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +# CONFIG_HW_PERF_EVENTS is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_UACCESS_WITH_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttymxc0,115200 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs video=mxcdi0fb:RGB24,800x600M-16@60" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_IMX=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_PM_RUNTIME=y +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y + +# +# CAN Device Drivers +# +# CONFIG_CAN_VCAN is not set +CONFIG_CAN_DEV=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_MCP251X=y +# CONFIG_CAN_SJA1000 is not set + +# +# CAN USB interfaces +# +# CONFIG_CAN_EMS_USB is not set +# CONFIG_CAN_DEBUG_DEVICES is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +# CONFIG_DEVTMPFS_MOUNT is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_MXC is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_MXC_M25P80 is not set +CONFIG_MTD_M25P80=y +# CONFIG_M25PXX_USE_FAST_READ is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_IMX_NFC=y +# CONFIG_MTD_NAND_MXC_V3 is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +CONFIG_SMSC_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_FEC=y +# CONFIG_FEC_1588 is not set +# CONFIG_FEC2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=y +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXC=y +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_P1003 is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +CONFIG_MXC_IIM=y +# CONFIG_MXS_VIIM is not set +# CONFIG_IMX_SIM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXC=y +CONFIG_SERIAL_MXC_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_IMX is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IMX=y +# CONFIG_I2C_MXC is not set +# CONFIG_I2C_MXC_HS is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_IMX_VER_0_7=y +CONFIG_SPI_IMX_VER_2_3=y +CONFIG_SPI_IMX=y +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_MXC is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +CONFIG_W1=y +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +CONFIG_W1_MASTER_MXC=y +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_GPIO is not set + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +CONFIG_W1_SLAVE_SMEM=y +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2751 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2438 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +CONFIG_APM_POWER=y +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_DS2438 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX17135 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_SENSORS_MAG3110 is not set +# CONFIG_MXC_MMA8450 is not set +# CONFIG_MXC_MMA8451 is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_MXC_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_IMX2_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_DUMMY=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_MC34708=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_IR_CORE=y +CONFIG_VIDEO_IR=y +# CONFIG_RC_MAP is not set +# CONFIG_IR_NEC_DECODER is not set +# CONFIG_IR_RC5_DECODER is not set +# CONFIG_IR_RC6_DECODER is not set +# CONFIG_IR_JVC_DECODER is not set +# CONFIG_IR_SONY_DECODER is not set +# CONFIG_IR_IMON is not set +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_CUSTOMISE=y +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +# CONFIG_MEDIA_TUNER_MAX2165 is not set +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_IR_I2C=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_MXC_CAMERA is not set +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +# CONFIG_VIDEO_MXC_OPL is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_V4L_USB_DRIVERS is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_TVOUT_TVE is not set +# CONFIG_FB_MXC_LDB is not set +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_DATAIMAGE_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_OPTREX_VGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SII902X is not set +# CONFIG_FB_MXC_CH7026 is not set +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +CONFIG_FB_MXC_FIX_SYNC_PANEL=y +# CONFIG_FB_MXC_ASYNC_PANEL is not set +# CONFIG_FB_MXC_EINK_PANEL is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_S6E63M0 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_MXC_SOC=y +CONFIG_SND_MXC_SOC_SSI=y +CONFIG_SND_MXC_SOC_IRAM=y +CONFIG_SND_SOC_IMX_3STACK_SGTL5000=y +# CONFIG_SND_SOC_IMX_3STACK_AK4647 is not set +# CONFIG_SND_SOC_IMX_3STACK_WM8580 is not set +# CONFIG_SND_SOC_IMX_3STACK_AK5702 is not set +# CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH is not set +# CONFIG_SND_SOC_IMX_3STACK_CS42888 is not set +# CONFIG_SND_SOC_IMX_SPDIF is not set +CONFIG_MXC_SSI_DUAL_FIFO=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_SGTL5000=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ARC is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_MXC=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +CONFIG_USB_GADGET_FSL_USB2=y +CONFIG_USB_FSL_USB2=y +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_ARC is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=y +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_MXC is not set +CONFIG_RTC_DRV_MXC_V2=y +# CONFIG_RTC_DRV_IMXDI is not set +CONFIG_RTC_MC13892=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_MXC_PXP=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +# CONFIG_TIMB_DMA is not set +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +# CONFIG_VIDEO_TM6000 is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_ECHO is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_TRANZPORT is not set +# CONFIG_POHMELFS is not set +# CONFIG_LINE6_USB is not set +# CONFIG_FB_UDL is not set + +# +# RAR Register Driver +# +# CONFIG_IIO is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_FB_SM7XX is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_ADIS16255 is not set + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3=y + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +CONFIG_MXC_PMIC_MC34708=y +CONFIG_MXC_PMIC_I2C=y +# CONFIG_MXC_PMIC_SPI is not set +# CONFIG_MXC_PMIC_MC34704 is not set +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +# CONFIG_MXC_MC13892_ADC is not set +# CONFIG_MXC_MC13892_RTC is not set +# CONFIG_MXC_MC13892_LIGHT is not set +# CONFIG_MXC_MC13892_BATTERY is not set +# CONFIG_MXC_MC13892_BACKUP_BATT is not set +# CONFIG_MXC_MC13892_CONNECTIVITY is not set +# CONFIG_MXC_MC13892_POWER is not set +# CONFIG_MXC_MC34708_ADC is not set +# CONFIG_MXC_MC34708_RTC is not set +# CONFIG_MXC_MC34708_BATTERY is not set +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_SCC2 is not set +# CONFIG_MXC_SECURITY_RNG is not set + +# +# SAHARA2 Security Hardware Support +# +# CONFIG_MXC_SAHARA is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +# CONFIG_MXC_VPU_DEBUG is not set + +# +# MXC Asynchronous Sample Rate Converter support +# + +# +# MXC Bluetooth support +# + +# +# Broadcom GPS ioctrl support +# + +# +# MXC Media Local Bus Driver +# + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC GPU support +# +CONFIG_MXC_AMD_GPU=y + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_FRAME_POINTER=y +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 2dc41de..d175de0 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -1,10 +1,14 @@ if ARCH_MX5 +config SOC_IMX51 + bool + config ARCH_MX51 bool select USB_ARCH_HAS_EHCI select MXC_TZIC select ARCH_MXC_IOMUX_V3 + select SOC_IMX51 config ARCH_MX53 bool @@ -42,6 +46,13 @@ config MACH_MX51_BABBAGE u-boot. This includes specific configurations for the board and its peripherals. +config MACH_VMX51 + bool "Support MX51 VMX platform" + select ARCH_MX51 + help + Include support for VMX51 platform. This includes specific + configurations for the board and its peripherals. + config MACH_MX53_EVK bool "Support MX53 EVK platform" select ARCH_MX53 @@ -120,4 +131,27 @@ config MXC_BLUETOOTH_RFKILL depends on RFKILL ---help--- Say Y to get the standard rfkill interface of Bluetooth + +config VMX_SPIMODULE + bool "Enable VMX51 SPI flash" + select SPI + select SPI_IMX + select EXPERIMENTAL + select MTD + select MTD_M25P80 + depends on MACH_VMX51 + help + This enables SPI eeprom platfrom device + + +config VMX_I2CMODULE + bool "Enable VMX51 I2C flash" + select I2C + select I2C_IMX + select MISC_DEVICES + select EEPROM_AT24 + depends on MACH_VMX51 + help + This enables I2C eeprom platfrom device + endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 96da373..965d823 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_MX50) += clock_mx50.o dmaengine.o dma-apbh.o mx50_suspend.o mx obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_pmic_mc13892.o +obj-$(CONFIG_MACH_VMX51) += mx51_vmx.o mx51_vmx_pmic_mc13892.o obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_pmic_mc13892.o obj-$(CONFIG_MACH_MX53_ARD) += mx53_ard.o mx53_ard_pmic_ltc3589.o obj-$(CONFIG_MACH_MX53_SMD) += mx53_smd.o mx53_smd_pmic_da9053.o diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index c051fd8..ce39a73 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -240,6 +240,22 @@ static unsigned long get_high_reference_clock_rate(struct clk *clk) return external_high_reference; } +static int high_reference_clock_rate_enable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg |= MXC_CCM_CCR_CAMP1_EN; + __raw_writel(reg, MXC_CCM_CCR); + + return 0; +} + +static void high_reference_clock_rate_disable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg &= ~MXC_CCM_CCR_CAMP1_EN; + __raw_writel(reg, MXC_CCM_CCR); +} + static unsigned long get_low_reference_clock_rate(struct clk *clk) { return external_low_reference; @@ -255,13 +271,37 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) return ckih2_reference; } +static int ckih2_reference_clock_rate_enable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg |= MXC_CCM_CCR_CAMP2_EN; + __raw_writel(reg, MXC_CCM_CCR); + + return 0; +} + +static void ckih2_reference_clock_rate_disable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg &= ~MXC_CCM_CCR_CAMP2_EN; + __raw_writel(reg, MXC_CCM_CCR); +} + +static struct clk dummy_clk = { + .id = 0, +}; + /* External high frequency clock */ static struct clk ckih_clk = { .get_rate = get_high_reference_clock_rate, + .enable = high_reference_clock_rate_enable, + .disable = high_reference_clock_rate_disable, }; static struct clk ckih2_clk = { .get_rate = get_ckih2_reference_clock_rate, + .enable = ckih2_reference_clock_rate_enable, + .disable = ckih2_reference_clock_rate_disable, }; static struct clk osc_clk = { @@ -3872,29 +3912,6 @@ static int _clk_vpu_set_parent(struct clk *clk, struct clk *parent) return 0; } -static int _clk_vpu_enable(struct clk *clk) -{ - /* Set VPU's parent to be axi_a or ahb when its enabled. */ - if (cpu_is_mx51()) { - clk_set_parent(&vpu_clk[0], &axi_a_clk); - clk_set_parent(&vpu_clk[1], &axi_a_clk); - } - - return _clk_enable(clk); - -} - -static void _clk_vpu_disable(struct clk *clk) -{ - _clk_disable(clk); - - /* Set VPU's parent to be axi_b when its disabled. */ - if (cpu_is_mx51()) { - clk_set_parent(&vpu_clk[0], &axi_b_clk); - clk_set_parent(&vpu_clk[1], &axi_b_clk); - } -} - static struct clk vpu_clk[] = { { .set_parent = _clk_vpu_set_parent, @@ -3907,10 +3924,10 @@ static struct clk vpu_clk[] = { }, { .set_parent = _clk_vpu_set_parent, - .enable = _clk_vpu_enable, + .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR5, .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, - .disable = _clk_vpu_disable, + .disable = _clk_disable, .secondary = &vpu_clk[2], }, { @@ -4041,7 +4058,7 @@ static struct clk sahara_clk[] = { .secondary = &sahara_clk[2], }, { - .parent = &scc_clk, + .parent = &scc_clk[0], .secondary = &emi_fast_clk, } }; @@ -4335,16 +4352,20 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "csi_mclk1", csi0_clk), _REGISTER_CLOCK(NULL, "csi_mclk2", csi1_clk), _REGISTER_CLOCK(NULL, "tve_clk", tve_clk), +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) // IMX + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk[0]), + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk[0]), + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk[0]), +#else // FSL _REGISTER_CLOCK("mxcintuart.0", NULL, uart1_clk[0]), _REGISTER_CLOCK("mxcintuart.1", NULL, uart2_clk[0]), _REGISTER_CLOCK("mxcintuart.2", NULL, uart3_clk[0]), - _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]), +#endif + _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]), // masu FIXME + _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk[0]), _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]), _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk[0]), _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk[0]), - _REGISTER_CLOCK("mxc_spi.0", NULL, cspi1_clk[0]), - _REGISTER_CLOCK("mxc_spi.1", NULL, cspi2_clk[0]), - _REGISTER_CLOCK("mxc_spi.2", NULL, cspi3_clk), _REGISTER_CLOCK(NULL, "ssi_lp_apm_clk", ssi_lp_apm_clk), _REGISTER_CLOCK("mxc_ssi.0", NULL, ssi1_clk[0]), _REGISTER_CLOCK("mxc_ssi.1", NULL, ssi2_clk[0]), @@ -4352,11 +4373,19 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "ssi_ext1_clk", ssi_ext1_clk), _REGISTER_CLOCK(NULL, "ssi_ext2_clk", ssi_ext2_clk), _REGISTER_CLOCK(NULL, "iim_clk", iim_clk), - _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]), + _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]), // FSL _REGISTER_CLOCK(NULL, "usb_ahb_clk", usb_ahb_clk), _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy_clk[0]), _REGISTER_CLOCK(NULL, "usb_utmi_clk", usb_utmi_clk), _REGISTER_CLOCK(NULL, "usb_clk", usb_clk), + _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk[0]), // IMX + _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk), + _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy_clk[0]), + _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk[0]), + _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk), + _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk[0]), + _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_ahb_clk), + _REGISTER_CLOCK("fsl-usb2-udc", "usb_phy1", usb_phy_clk[0]), _REGISTER_CLOCK("mxsdhci.0", NULL, esdhc1_clk[0]), _REGISTER_CLOCK("mxsdhci.1", NULL, esdhc2_clk[0]), _REGISTER_CLOCK("mxsdhci.2", NULL, esdhc3_clk[0]), @@ -4387,6 +4416,17 @@ static struct clk_lookup lookups[] = { static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("mxc_i2c_hs.3", NULL, hsi2c_serial_clk), + _REGISTER_CLOCK("mxc_keypad.0", "kpp_clk", dummy_clk), + _REGISTER_CLOCK(NULL, "wdog_clk", dummy_clk), +#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) // IMX + _REGISTER_CLOCK("imx51-ecspi.0", NULL, cspi1_clk[0]), + _REGISTER_CLOCK("imx51-ecspi.1", NULL, cspi2_clk[0]), + _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi3_clk), +#else // FSL + _REGISTER_CLOCK("mxc_spi.0", NULL, cspi1_clk[0]), + _REGISTER_CLOCK("mxc_spi.1", NULL, cspi2_clk[0]), + _REGISTER_CLOCK("mxc_spi.2", NULL, cspi3_clk), +#endif _REGISTER_CLOCK("mxc_sim.0", NULL, sim_clk[0]), _REGISTER_CLOCK("mxc_alsa_spdif.0", NULL, spdif1_clk[0]), _REGISTER_CLOCK(NULL, "mipi_hsp_clk", mipi_hsp_clk), @@ -4477,7 +4517,7 @@ static void clk_tree_init(void) } } - +#ifdef CONFIG_ARCH_MX51 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) { __iomem void *base; @@ -4623,8 +4663,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long /* Initialise the parents to be axi_b, parents are set to * axi_a when the clocks are enabled. */ - clk_set_parent(&vpu_clk[0], &axi_b_clk); - clk_set_parent(&vpu_clk[1], &axi_b_clk); + clk_set_parent(&vpu_clk[0], &axi_a_clk); + clk_set_parent(&vpu_clk[1], &axi_a_clk); clk_set_parent(&gpu3d_clk[0], &axi_a_clk); clk_set_parent(&gpu2d_clk, &axi_a_clk); @@ -4789,7 +4829,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); return 0; } +#endif +#ifdef CONFIG_ARCH_MX53 int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) { __iomem void *base; @@ -5055,6 +5097,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); return 0; } +#endif /*! * Setup cpu clock based on working point. diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 591d729..a824d75 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -606,7 +606,11 @@ static struct resource mxcspi1_resources[] = { static u64 spi_dma_mask = DMA_BIT_MASK(32); struct platform_device mxcspi1_device = { +#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) + .name = "imx51-ecspi", +#else .name = "mxc_spi", +#endif .id = 0, .num_resources = ARRAY_SIZE(mxcspi1_resources), .resource = mxcspi1_resources, @@ -635,7 +639,11 @@ static struct resource mxcspi2_resources[] = { }; struct platform_device mxcspi2_device = { +#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) + .name = "imx51-ecspi", +#else .name = "mxc_spi", +#endif .id = 1, .num_resources = ARRAY_SIZE(mxcspi2_resources), .resource = mxcspi2_resources, @@ -659,12 +667,76 @@ static struct resource mxcspi3_resources[] = { }; struct platform_device mxcspi3_device = { +#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) + .name = "imx51-cspi", +#else .name = "mxc_spi", +#endif .id = 2, .num_resources = ARRAY_SIZE(mxcspi3_resources), .resource = mxcspi3_resources, }; +static struct resource mxcuart1_resources[] = { + { + .start = UART1_BASE_ADDR, + .end = UART1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_UART1, + .end = MXC_INT_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource mxcuart2_resources[] = { + { + .start = UART2_BASE_ADDR, + .end = UART2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_UART2, + .end = MXC_INT_UART2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource mxcuart3_resources[] = { + { + .start = UART3_BASE_ADDR, + .end = UART3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_UART3, + .end = MXC_INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxcuart_devices[] = { + { + .name = "imx-uart", + .id = 0, + .num_resources = ARRAY_SIZE(mxcuart1_resources), + .resource = mxcuart1_resources, + }, + { + .name = "imx-uart", + .id = 1, + .num_resources = ARRAY_SIZE(mxcuart2_resources), + .resource = mxcuart2_resources, + }, + { + .name = "imx-uart", + .id = 2, + .num_resources = ARRAY_SIZE(mxcuart3_resources), + .resource = mxcuart3_resources, + }, +}; + static struct resource mxci2c1_resources[] = { { .start = I2C1_BASE_ADDR, @@ -1261,7 +1333,11 @@ struct platform_device mxc_usbdr_otg_device = { }; struct platform_device mxc_usbdr_host_device = { +#if defined(CONFIG_USB_EHCI_ARC) || defined(CONFIG_USB_EHCI_ARC_MODULE) .name = "fsl-ehci", +#else + .name = "mxc-ehci", +#endif .id = 0, .num_resources = ARRAY_SIZE(usbotg_host_resources), .resource = usbotg_host_resources, @@ -1302,7 +1378,11 @@ static struct resource usbh1_wakeup_resources[] = { }; struct platform_device mxc_usbh1_device = { +#if defined(CONFIG_USB_EHCI_ARC) || defined(CONFIG_USB_EHCI_ARC_MODULE) .name = "fsl-ehci", +#else + .name = "mxc-ehci", +#endif .id = 1, .num_resources = ARRAY_SIZE(usbh1_resources), .resource = usbh1_resources, diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index 3927383..81c3770 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -40,6 +40,7 @@ extern struct platform_device mxcscc_device; extern struct platform_device mxcspi1_device; extern struct platform_device mxcspi2_device; extern struct platform_device mxcspi3_device; +extern struct platform_device mxcuart_devices[]; extern struct platform_device mxci2c_devices[]; extern struct platform_device mxci2c_hs_device; extern struct platform_device mxc_tve_device; diff --git a/arch/arm/mach-mx5/mx51_vmx.c b/arch/arm/mach-mx5/mx51_vmx.c index e69de29..2305bd2 100644 --- a/arch/arm/mach-mx5/mx51_vmx.c +++ b/arch/arm/mach-mx5/mx51_vmx.c @@ -0,0 +1,1722 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011 Voipac a.s., All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "crm_regs.h" +#include "usb.h" + +/*! + * @file mach-mx51/mx51_vmx.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX51 + */ + +// OSC +#define VMX51_OSC_EN (2*32 + 25) /* GPIO3_25 */ +#define VMX51_PER_RST (2*32 + 2) /* GPIO3_2 */ + +// PMIC +#define VMX51_PMIC_INT (0*32 + 3) /* GPIO1_3 */ +#define VMX51_PMIC_WDI (0*32 + 4) /* GPIO1_4 */ +#define VMX51_PWR_BTN (0*32 + 1) /* GPIO1_1 */ + +// SPI +#define VMX51_ECSPI1_CS0 (3*32 + 24) /* GPIO4_24 */ +#define VMX51_ECSPI1_CS1 (3*32 + 25) /* GPIO4_25 */ +#define VMX51_TSC2046_IRQ (1*32 + 7) /* GPIO2_7 */ +#define VMX51_TSC2046_CS (2*32 + 6) /* GPIO3_6 */ +#define VMX51_MCP2515_IRQ (1*32 + 6) /* GPIO2_6 */ +#define VMX51_MCP2515_CS (2*32 + 5) /* GPIO3_5 */ + +// SD +#define VMX51_SD1_CD (2*32 + 28) /* GPIO3_28 */ +//#define VMX51_SD1_WP (0) /* NO GPIO */ +#define VMX51_SD2_CD (2*32 + 27) /* GPIO3_27 */ +#define VMX51_SD2_WP (2*32 + 0) /* GPIO3_0 */ + +// USB +#define VMX51_USBH1_OC (0*32 + 6) /* GPIO1_6 */ +#define VMX51_USBH1_PHY_RST (0*32 + 7) /* GPIO1_7 */ +#define VMX51_USB0_PEN (0*32 + 8) /* GPIO1_8 */ +#define VMX51_USB0_OC (0*32 + 9) /* GPIO1_9 */ + +// FEC +#define VMX51_FEC_RST (2*32 + 30) /* GPIO3_30 */ + +// LED +#define VMX51_LED_RED (1*32 + 4) /* GPIO2_4 */ +#define VMX51_LED_ORANGE (1*32 + 5) /* GPIO2_5 */ + +// DISP +#define VMX51_LCD_PSAVE (2*32 + 8) /* GPIO3_8 */ + +// FM +#define VMX51_FM_IRQ (2*32 + 4) /* GPIO3_4 */ + +// SCR +#define VMX51_SCR_RST (2*32 + 7) /* GPIO3_7 */ + + +// Defines +#define MHZ(a) KHZ2PICOS(a*1000) +#define KHZ(a) KHZ2PICOS(a) + +// Fix spi and nand naming collision +//#include +struct spi_flash_platform_data { + char *name; + struct mtd_partition *parts; + unsigned int nr_parts; + char *type; +}; + +extern int __init mx51_vmx_init_mc13892(void); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +extern struct dvfs_wp *(*get_dvfs_core_wp)(int *wp); + +static int num_cpu_wp; + +static iomux_v3_cfg_t vmx51_pads[] = { + /* OSC */ + MX51_PAD_NANDF_D15__GPIO3_25, /* CKIH1_EN + USB PHY CLK */ + + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* UART2 */ + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + MX51_PAD_EIM_D26__UART2_RTS, + MX51_PAD_EIM_D25__UART2_CTS, + + /* UART3 */ + MX51_PAD_UART3_RXD__UART3_RXD, + MX51_PAD_UART3_TXD__UART3_TXD, + MX51_PAD_EIM_D18__UART3_RTS, + MX51_PAD_EIM_D17__UART3_CTS, + + /* I2C1 */ + MX51_PAD_EIM_D16__I2C1_SDA, + MX51_PAD_EIM_D19__I2C1_SCL, + + /* I2C2 */ + MX51_PAD_EIM_D24__I2C2_SDA, + MX51_PAD_EIM_D27__I2C2_SCL, + + /* CSPI1 */ + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_RDY__ECSPI1_RDY, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + + /* SD1 */ + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + + /* GPIO SD1 */ + MX51_PAD_NANDF_D12__GPIO3_28, /* SD1_CD */ + + /* SD2 */ + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + + /* GPIO SD2 */ + MX51_PAD_NANDF_D13__GPIO3_27, /* SD2_CD */ + MX51_PAD_DI1_PIN11__GPIO3_0, /* SD2_WP */ + + /* Touch */ + MX51_PAD_EIM_D23__GPIO2_7, /* GPIO IRQ */ + MX51_PAD_DISPB2_SER_DIO__GPIO3_6, /* SPI CS */ + + /* Can */ + MX51_PAD_EIM_D22__GPIO2_6, /* GPIO_IRQ */ + MX51_PAD_DISPB2_SER_DIN__GPIO3_5, /* SPI CS */ + + /* USB HOST1 */ + MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + + /* GPIO USB */ + MX51_PAD_GPIO1_6__GPIO1_6, /* USBH1_OC */ + MX51_PAD_GPIO1_7__GPIO1_7, /* USBH1_RST */ +// MX51_PAD_GPIO1_8__USB_PWR, + MX51_PAD_GPIO1_8__GPIO1_8, /* USB0_PEN */ +// MX51_PAD_GPIO1_9__USB_OC, + MX51_PAD_GPIO1_9__GPIO1_9, /* USB0_OC */ + + /* NANDF */ + MX51_PAD_NANDF_WE_B__NANDF_WE_B, + MX51_PAD_NANDF_RE_B__NANDF_RE_B, + MX51_PAD_NANDF_ALE__NANDF_ALE, + MX51_PAD_NANDF_CLE__NANDF_CLE, + MX51_PAD_NANDF_WP_B__NANDF_WP_B, + MX51_PAD_NANDF_RB0__NANDF_RB0, + MX51_PAD_NANDF_CS0__NANDF_CS0, + MX51_PAD_NANDF_D0__NANDF_D0, + MX51_PAD_NANDF_D1__NANDF_D1, + MX51_PAD_NANDF_D2__NANDF_D2, + MX51_PAD_NANDF_D3__NANDF_D3, + MX51_PAD_NANDF_D4__NANDF_D4, + MX51_PAD_NANDF_D5__NANDF_D5, + MX51_PAD_NANDF_D6__NANDF_D6, + MX51_PAD_NANDF_D7__NANDF_D7, + + /* FEC */ + MX51_PAD_EIM_EB2__FEC_MDIO, + MX51_PAD_EIM_EB3__FEC_RDATA1, + MX51_PAD_EIM_CS2__FEC_RDATA2, + MX51_PAD_EIM_CS3__FEC_RDATA3, + MX51_PAD_EIM_CS4__FEC_RX_ER, + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_NANDF_D11__FEC_RX_DV, + MX51_PAD_NANDF_D9__FEC_RDATA0, + MX51_PAD_NANDF_D8__FEC_TDATA0, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_NANDF_CS3__FEC_MDC, + MX51_PAD_NANDF_CS4__FEC_TDATA1, + MX51_PAD_NANDF_CS5__FEC_TDATA2, + MX51_PAD_NANDF_CS6__FEC_TDATA3, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + MX51_PAD_NANDF_RB2__FEC_COL, + MX51_PAD_NANDF_RB3__FEC_RX_CLK, + + /* GPIO FEC */ + MX51_PAD_NANDF_D10__GPIO3_30, + + /* KEYPAD */ + MX51_PAD_KEY_ROW0__KEY_ROW0, + MX51_PAD_KEY_ROW1__KEY_ROW1, + MX51_PAD_KEY_ROW2__KEY_ROW2, + MX51_PAD_KEY_ROW3__KEY_ROW3, + MX51_PAD_KEY_COL0__KEY_COL0, + MX51_PAD_KEY_COL1__KEY_COL1, + MX51_PAD_KEY_COL2__KEY_COL2, + MX51_PAD_KEY_COL3__KEY_COL3, + MX51_PAD_KEY_COL4__KEY_COL4, + MX51_PAD_KEY_COL5__KEY_COL5, + + /* GPIO LED */ + MX51_PAD_EIM_D20__GPIO2_4, + MX51_PAD_EIM_D21__GPIO2_5, + + /* DISP1 */ + MX51_PAD_DISP1_DAT0__DISP1_DAT0, + MX51_PAD_DISP1_DAT1__DISP1_DAT1, + MX51_PAD_DISP1_DAT2__DISP1_DAT2, + MX51_PAD_DISP1_DAT3__DISP1_DAT3, + MX51_PAD_DISP1_DAT4__DISP1_DAT4, + MX51_PAD_DISP1_DAT5__DISP1_DAT5, + MX51_PAD_DISP1_DAT6__DISP1_DAT6, + MX51_PAD_DISP1_DAT7__DISP1_DAT7, + MX51_PAD_DISP1_DAT8__DISP1_DAT8, + MX51_PAD_DISP1_DAT9__DISP1_DAT9, + MX51_PAD_DISP1_DAT10__DISP1_DAT10, + MX51_PAD_DISP1_DAT11__DISP1_DAT11, + MX51_PAD_DISP1_DAT12__DISP1_DAT12, + MX51_PAD_DISP1_DAT13__DISP1_DAT13, + MX51_PAD_DISP1_DAT14__DISP1_DAT14, + MX51_PAD_DISP1_DAT15__DISP1_DAT15, + MX51_PAD_DISP1_DAT16__DISP1_DAT16, + MX51_PAD_DISP1_DAT17__DISP1_DAT17, + MX51_PAD_DISP1_DAT18__DISP1_DAT18, + MX51_PAD_DISP1_DAT19__DISP1_DAT19, + MX51_PAD_DISP1_DAT20__DISP1_DAT20, + MX51_PAD_DISP1_DAT21__DISP1_DAT21, + MX51_PAD_DISP1_DAT22__DISP1_DAT22, + MX51_PAD_DISP1_DAT23__DISP1_DAT23, + MX51_PAD_DI1_PIN2__DI1_PIN2, + MX51_PAD_DI1_PIN3__DI1_PIN3, +// MX51_PAD_DI1_PIN15__DI1_PIN15, /* no mux */ +// MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK, /* no mux */ + + /* GPIO DISP1 */ + MX51_PAD_DISPB2_SER_RS__GPIO3_8, /* GPIO11 PSAVE */ + + /* PWM */ + MX51_PAD_GPIO1_2__PWM1_PWMO, + + /* OWIRE */ + MX51_PAD_OWIRE_LINE__OWIRE_LINE, + + /* CSI */ + MX51_PAD_CSI2_D12__CSI2_D12, + MX51_PAD_CSI2_D13__CSI2_D13, + MX51_PAD_CSI2_D14__CSI2_D14, + MX51_PAD_CSI2_D15__CSI2_D15, + MX51_PAD_CSI2_D16__CSI2_D16, + MX51_PAD_CSI2_D17__CSI2_D17, + MX51_PAD_CSI2_D18__CSI2_D18, + MX51_PAD_CSI2_D19__CSI2_D19, + MX51_PAD_CSI2_VSYNC__CSI2_VSYNC, + MX51_PAD_CSI2_HSYNC__CSI2_HSYNC, + MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK, + MX51_PAD_GPIO1_5__CSI2_MCLK, + + /* SSI1 */ + MX51_PAD_AUD3_BB_TXD__AUD3_TXD, + MX51_PAD_AUD3_BB_RXD__AUD3_RXD, + MX51_PAD_AUD3_BB_CK__AUD3_TXC, + MX51_PAD_AUD3_BB_FS__AUD3_TXFS, + + /* SSI1 GPIO */ + MX51_PAD_DI1_D0_CS__GPIO3_3, + + /* SSI2 */ + MX51_PAD_EIM_D28__AUD6_TXD, + MX51_PAD_EIM_D29__AUD6_RXD, + MX51_PAD_EIM_D30__AUD6_TXC, + MX51_PAD_EIM_D31__AUD6_TXFS, + + /* SSI2 GPIO */ + MX51_PAD_DI1_D1_CS__GPIO3_4, + + /* EIM */ + MX51_PAD_EIM_CS0__EIM_CS0, + MX51_PAD_EIM_CS1__EIM_CS1, +// MX51_PAD_EIM_WAIT__EIM_WAIT, /* no muxing */ +// MX51_PAD_EIM_RW__EIM_RW, /* no muxing */ + MX51_PAD_EIM_EB0__EIM_EB0, + MX51_PAD_EIM_EB1__EIM_EB1, + MX51_PAD_EIM_OE__EIM_OE, + MX51_PAD_EIM_LBA__EIM_LBA, + + MX51_PAD_EIM_A16__EIM_A16, + MX51_PAD_EIM_A17__EIM_A17, + MX51_PAD_EIM_A18__EIM_A18, + MX51_PAD_EIM_A19__EIM_A19, + MX51_PAD_EIM_A20__EIM_A20, + MX51_PAD_EIM_A21__EIM_A21, + MX51_PAD_EIM_A22__EIM_A22, + MX51_PAD_EIM_A23__EIM_A23, + MX51_PAD_EIM_A24__EIM_A24, + MX51_PAD_EIM_A25__EIM_A25, + MX51_PAD_EIM_A26__EIM_A26, + MX51_PAD_EIM_A27__EIM_A27, + + MX51_PAD_EIM_DA0__EIM_DA0, + MX51_PAD_EIM_DA1__EIM_DA1, + MX51_PAD_EIM_DA2__EIM_DA2, + MX51_PAD_EIM_DA3__EIM_DA3, + MX51_PAD_EIM_DA4__EIM_DA4, + MX51_PAD_EIM_DA5__EIM_DA5, + MX51_PAD_EIM_DA6__EIM_DA6, + MX51_PAD_EIM_DA7__EIM_DA7, + MX51_PAD_EIM_DA8__EIM_DA8, + MX51_PAD_EIM_DA9__EIM_DA9, + MX51_PAD_EIM_DA10__EIM_DA10, + MX51_PAD_EIM_DA11__EIM_DA11, + MX51_PAD_EIM_DA12__EIM_DA12, + MX51_PAD_EIM_DA13__EIM_DA13, + MX51_PAD_EIM_DA14__EIM_DA14, + MX51_PAD_EIM_DA15__EIM_DA15, + + /* GPIO */ + MX51_PAD_GPIO1_0__GPIO1_0, /* GPIO0 msp430 i2c int */ + MX51_PAD_GPIO1_1__GPIO1_1, /* GPIO1 temporary PWR button */ + MX51_PAD_DI1_PIN12__GPIO3_1, /* GPIO7 NC */ + MX51_PAD_DISPB2_SER_CLK__GPIO3_7, /* GPIO10 smard card reader rst */ + + /* MISC */ + MX51_PAD_DI1_PIN13__GPIO3_2, /* RESET_OUT peripheral reset */ + + /* PMIC */ + MX51_PAD_GPIO1_3__GPIO1_3, /* PMIC_INT */ + MX51_PAD_GPIO1_4__GPIO1_4, /* PMIC WDI */ + + /* UNCONNECTED */ + MX51_PAD_EIM_DTACK__EIM_DTACK, /* selected by R900 */ +// MX51_PAD_EIM_CRE__EIM_CRE, /* unconnected */ +// MX51_PAD_I2C1_CLK__GPIO4_16, /* unconnected */ +// MX51_PAD_I2C1_DAT__GPIO4_17, /* unconnected */ +// MX51_PAD_NANDF_D14__GPIO3_26, /* unconnected */ +// MX51_PAD_NANDF_CS1__GPIO3_17, /* unconnected */ +// MX51_PAD_NANDF_RB1__GPIO3_9, /* unconnected */ +// MX51_PAD_GPIO_NAND__GPIO_NAND, /* unconnected */ +}; + +static struct dvfs_wp dvfs_core_setpoint[] = { + {33, 13, 33, 10, 10, 0x08}, /* 800MHz */ + {28, 8, 33, 10, 10, 0x08}, /* 400MHz */ + {20, 0, 33, 20, 10, 0x08}, /* 160MHz */ + {28, 8, 33, 20, 30, 0x08}, /* 160MHz, AHB 133MHz, LPAPM mode */ + {29, 0, 33, 20, 10, 0x08},}; /* 160MHz, AHB 24MHz */ + +/* CPU working point(wp) */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 1000000000, + .cpu_rate = 1000000000, + .pdf = 0, + .mfi = 10, + .mfd = 11, + .mfn = 5, + .cpu_podf = 0, + .cpu_voltage = 1175000,}, + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1100000,}, + { + .pll_rate = 800000000, + .cpu_rate = 400000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 1, + .cpu_voltage = 950000,}, + { + .pll_rate = 800000000, + .cpu_rate = 166250000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 4, + .cpu_voltage = 850000,}, +}; + +static struct fb_videomode video_modes[] = { + { + // NTSC TV output + .name ="TV-NTSC", + .refresh = 60, + .xres = 720, + .yres = 480, + .pixclock = KHZ(27700), + .left_margin = 96, // Back porch + .right_margin = 24, // Front porch + .upper_margin = 32, // Back porch + .lower_margin = 10, // Front porch + .hsync_len = 40, + .vsync_len = 3, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_INTERLACED, + .flag = 0, + }, + { + // PAL TV output + .name ="TV-PAL", + .refresh = 50, + .xres = 720, + .yres = 576, + .pixclock = 74074, + .left_margin = 132, + .right_margin = 11, + .upper_margin = 22, + .lower_margin = 26, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST, + .flag = 0, + }, + { + // 720p60 TV output + .name ="720P60", + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = KHZ(74200), + .left_margin = 216, // Back porch + .right_margin = 72, // Front porch + .upper_margin = 22, // Back porch + .lower_margin = 3, // Front porch + .hsync_len = 80, + .vsync_len = 5, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, + { + // DVI panel + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ(25175), + .left_margin = 48, // Back porch + .right_margin = 16, // Front porch + .upper_margin = 33, // Back porch + .lower_margin = 10, // Front porch + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, + { + // DVI panel + .name = "SVGA", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = MHZ(40), + .left_margin = 88, // Back porch + .right_margin = 40, // Front porch + .upper_margin = 23, // Back porch + .lower_margin = 2, // Front porch + .hsync_len = 128, + .vsync_len = 5, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, + { + // DVI panel + .name = "XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = MHZ(65), + .left_margin = 160, // Back porch + .right_margin = 24, // Front porch + .upper_margin = 29, // Back porch + .lower_margin = 3, // Front porch + .hsync_len = 136, + .vsync_len = 6, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, + { + // DVI panel + .name = "WXGA", + .refresh = 60, + .xres = 1280, + .yres = 800, + .pixclock = KHZ(83460), + .left_margin = 200, // Back porch + .right_margin = 64, // Front porch + .upper_margin = 24, // Back porch + .lower_margin = 1, // Front porch + .hsync_len = 136, + .vsync_len = 3, + .sync = FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +#if !defined(FB_MXC_DATAIMAGE_WVGA_SYNC_PANEL) + { + // FG0700K5DSSWAGT1 + .name = "WVGA", + .refresh = 59, + .xres = 800, + .yres = 480, + .pixclock = KHZ(33260), + .left_margin = 160, // Back porch + .right_margin = 54, // Front porch + .upper_margin = 10, // Back porch + .lower_margin = 10, // Front porch + .hsync_len = 86, + .vsync_len = 4, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +#endif +#if !defined(FB_MXC_OPTREX_VGA_SYNC_PANEL) + { + // t-51750gd065j-lw + .name = "VGA-lcd", + .refresh = 59, + .xres = 640, + .yres = 480, + .pixclock = KHZ(24000), + .left_margin = 84, // Back porch + .right_margin = 10, // Front porch + .upper_margin = 20, // Back porch + .lower_margin = 20, // Front porch + .hsync_len = 34, + .vsync_len = 5, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + + }, +#endif +}; + +static struct dvfs_wp *mx51_vmx_get_dvfs_core_table(int *wp) +{ + *wp = ARRAY_SIZE(dvfs_core_setpoint); + return dvfs_core_setpoint; +} + +struct cpu_wp *mx51_vmx_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_auto; +} + +void mx51_vmx_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) +static struct imxuart_platform_data uart1_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct imxuart_platform_data uart2_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct imxuart_platform_data uart3_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; +#endif // CONFIG_SERIAL_IMX + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static u16 keymapping[16] = { + KEY_RESERVED, KEY_HOME, KEY_RESERVED, KEY_BACK, + KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, + KEY_RESERVED, KEY_MENU, KEY_RESERVED, KEY_ZOOM, + KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, +}; + +static struct keypad_data keypad_plat_data = { + .rowmax = 4, + .colmax = 4, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + +static struct gpio_led vmx_leds[] = { + { + .name = "red", + .default_trigger = "heartbeat", + .gpio = VMX51_LED_RED, + }, + { + .name = "orange", + .default_trigger = "none", + .gpio = VMX51_LED_ORANGE, + } +}; + +static struct gpio_led_platform_data vmx_led_data = { + .leds = vmx_leds, + .num_leds = ARRAY_SIZE(vmx_leds), +}; + +static struct platform_device vmx_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &vmx_led_data, + }, +}; + +static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 50000, +}; + +extern void mx5_ipu_reset(void); +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 2, + .reset = mx5_ipu_reset, +}; + +extern void mx5_vpu_reset(void); +static struct mxc_vpu_platform_data mxc_vpu_data = { + .iram_enable = false, + .iram_size = 0x14000, + .reset = mx5_vpu_reset, +}; + +/* Internal i2c bus */ +static struct imxi2c_platform_data mxci2c1_data = { + .bitrate = 400000, +}; + +/* External i2c bus */ +static struct imxi2c_platform_data mxci2c2_data = { + .bitrate = 100000, +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "SW1", + .lp_reg_id = "SW2", +}; + +static struct mxc_dvfsper_data dvfs_per_data = { + .reg_id = "SW2", + .clk_id = "gpc_dvfs_clk", + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .gpc_adu = 0x0, + .vai_mask = MXC_DVFSPMCR0_FSVAI_MASK, + .vai_offset = MXC_DVFSPMCR0_FSVAI_OFFSET, + .dvfs_enable_bit = MXC_DVFSPMCR0_DVFEN, + .irq_mask = MXC_DVFSPMCR0_FSVAIM, + .div3_offset = 0, + .div3_mask = 0x7, + .div3_div = 2, + .lp_high = 1250000, + .lp_low = 1250000, +}; + +/* NAND Flash Partitions */ +#ifdef CONFIG_MTD_PARTITIONS + +static struct mtd_partition nand_flash_partitions[] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 256 * 1024}, + { + .name = "nand.bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 768 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 3 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +#endif + +#if defined(CONFIG_MTD_NAND_MXC_V3) || defined(CONFIG_MTD_NAND_MXC_V3_MODULE) +static int nand_init(void) +{ + /* Configure the pins */ + return 0; +} + +static void nand_exit(void) +{ + /* Free the pins */ + ; +} + +static struct flash_platform_data mxc_nand_data = { +#ifdef CONFIG_MTD_PARTITIONS + .parts = nand_flash_partitions, + .nr_parts = ARRAY_SIZE(nand_flash_partitions), +#endif // CONFIG_MTD_PARTITIONS + .width = 1, + .init = nand_init, + .exit = nand_exit, +}; +#endif // CONFIG_MTD_NAND_MXC_V3 + +/* i.MX MTD NAND Flash Controller */ + +#if defined(CONFIG_MTD_NAND_IMX_NFC) || defined(CONFIG_MTD_NAND_IMX_NFC_MODULE) +/* + * Platform-specific information about this device. Some of the details depend + * on the SoC. See imx_init_nfc() below for code that fills in the rest. + */ + +static struct imx_nfc_platform_data imx_nfc_platform_data = { + .nfc_major_version = 3, + .nfc_minor_version = 2, + .force_ce = false, + .target_cycle_in_ns = 30, + .clock_name = "nfc_clk", + .set_page_size = 0, + .interleave = false, +#ifdef CONFIG_MTD_PARTITIONS + .partitions = nand_flash_partitions, + .partition_count = ARRAY_SIZE(nand_flash_partitions), +#endif // CONFIG_MTD_PARTITIONS +}; +#endif // CONFIG_MTD_NAND_IMX_NFC + +#if defined(FB_MXC_DATAIMAGE_WVGA_SYNC_PANEL) +static struct platform_device lcd_wvga_device = { + .name = "lcd_dataimage", +}; +#else +static struct platform_device lcd_vga_device = { + .name = "lcd_optrex", // default +}; +#endif + +static struct resource mxcfb_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = IPU_PIX_FMT_RGB24, +// .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "1024x768-16@60", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +static void mxc_iim_enable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + /* Enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg |= 0x10; + writel(reg, ccm_base + 0x64); +} + +static void mxc_iim_disable_fuse(void) +{ + u32 reg; + + /* Disable fuse blown */ + if (!ccm_base) + return; + + reg = readl(ccm_base + 0x64); + reg &= ~0x10; + writel(reg, ccm_base + 0x64); +} + +static struct mxc_iim_data iim_data = { + .bank_start = MXC_IIM_MX51_BANK_START_ADDR, + .bank_end = MXC_IIM_MX51_BANK_END_ADDR, + .enable_fuse = mxc_iim_enable_fuse, + .disable_fuse = mxc_iim_disable_fuse, +}; + +static int __init mxc_init_fb(void) +{ + if (!machine_is_vmx51()) + return -1; + +#if defined(FB_MXC_DATAIMAGE_WVGA_SYNC_PANEL) + mxc_register_device(&lcd_wvga_device, NULL); +#else + mxc_register_device(&lcd_vga_device, NULL); // default lcd +#endif + + /* DI0 -> DP-BG channel: */ + mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[0].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + + /* DI1 -> DC channel: */ +// mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); // MASU FIXME vmx51 have no second iface + + /* DI0/1 DP-FG channel: */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +device_initcall(mxc_init_fb); + +#if defined(CONFIG_VMX_I2CMODULE) +static struct at24_platform_data module_eeprom = { + .byte_len = SZ_512K / 8, + .page_size = 128, + .flags = AT24_FLAG_ADDR16, +}; +#endif // CONFIG_VMX_I2CMODULE + +static struct at24_platform_data bboard_eeprom = { + .byte_len = SZ_512K / 8, + .page_size = 128, + .flags = AT24_FLAG_ADDR16, +}; + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + I2C_BOARD_INFO("sgtl5000-i2c", 0x0a), + }, + { + I2C_BOARD_INFO("radio-si4705", 0x63), // FIXME DRIVER +// .irq = gpio_to_irq(RADIO_SI4705_IRQ), + }, + { + I2C_BOARD_INFO("24c512", 0x57), + .platform_data = &bboard_eeprom, + }, + { + I2C_BOARD_INFO("ds1339", 0x68), + }, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { +#if defined(CONFIG_VMX_I2CMODULE) + { + I2C_BOARD_INFO("24c512", 0x56), + .platform_data = &module_eeprom, + }, +#endif // CONFIG_VMX_I2CMODULE +}; + +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition mxc_spi_bbflash_partitions[] = { + { + .name = "spi.bbboot", + .offset = 0, + .size = 0x00040000, + .mask_flags = MTD_CAP_ROM, + }, + { + .name = "spi.bbkernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition mxc_spi_moflash_partitions[] = { + { + .name = "spi.moboot", + .offset = 0, + .size = 0x00040000, + .mask_flags = MTD_CAP_ROM, + }, + { + .name = "spi.mokernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; +#endif + +static struct spi_flash_platform_data mxc_spi_bbflash_data = { + .name = "m25p80", +#ifdef CONFIG_MTD_PARTITIONS + .parts = mxc_spi_bbflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_spi_bbflash_partitions), +#endif + .type = "sst25vf032b", +}; + +static struct spi_flash_platform_data mxc_spi_moflash_data = { + .name = "m25p80", +#ifdef CONFIG_MTD_PARTITIONS + .parts = mxc_spi_moflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_spi_moflash_partitions), +#endif + .type = "at25df081", +}; +#endif // CONFIG_MTD_M25P80 + +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) +static int ads7846_get_pendown_state(void) +{ + return !gpio_get_value(VMX51_TSC2046_IRQ); +} + +static struct ads7846_platform_data ads7846_config __initdata = { + .model = 7846, + .vref_delay_usecs = 100, + .x_plate_ohms = 300, + .y_plate_ohms = 600, + /* debounce Filter */ + .debounce_max = 10, /* max number of additional readings per sample */ + .debounce_rep = 1, /* additional consecutive good readings required after the first two */ + .debounce_tol = 5, /* tolerance used for filtering */ + + .get_pendown_state = ads7846_get_pendown_state, + .keep_vref_on = 1, + .vref_mv = 2500, +}; +#endif // CONFIG_TOUCHSCREEN_ADS7846 + +#if defined(CONFIG_CAN_MCP251X) || defined(CONFIG_CAN_MCP251X_MODULE) +static struct mcp251x_platform_data mcp251x_config = { + .oscillator_frequency = 16000000, + .model = CAN_MCP251X_MCP2515, + .board_specific_setup = NULL, + .power_enable = NULL, + .transceiver_enable = NULL, +}; +#endif // CONFIG_CAN_MCP251X + +static struct spi_board_info mxc_ecspi1_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) + { + .modalias = "m25p80", + .bus_num = 0, + .max_speed_hz = 80000000, /* max spi clock (SCK) speed in HZ */ + .chip_select = 0, + .platform_data = &mxc_spi_bbflash_data, + .mode = SPI_MODE_0, + }, +#if defined(CONFIG_VMX_SPIMODULE) + { + .modalias = "m25p80", + .bus_num = 0, + .max_speed_hz = 66000000, /* max spi clock (SCK) speed in HZ */ + .chip_select = 1, + .platform_data = &mxc_spi_moflash_data, + .mode = SPI_MODE_0, + }, +#endif // CONFIG_VMX_SPIMODULE +#endif // CONFIG_MTD_M25P80 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) + { + .modalias = "ads7846", // MASU FIXME regulator + .bus_num = 0, + .max_speed_hz = (125000 * 26), /* AD speed x (cmd + sample + before, after)*/ + .irq = gpio_to_irq(VMX51_TSC2046_IRQ), + .chip_select = 2, + .platform_data = &ads7846_config, + .mode = SPI_MODE_2, + }, +#endif // CONFIG_TOUCHSCREEN_ADS7846 +#if defined(CONFIG_CAN_MCP251X) || defined(CONFIG_CAN_MCP251X_MODULE) + { + .modalias = "mcp251x", + .bus_num = 0, + .max_speed_hz = 10000000, + .irq = gpio_to_irq(VMX51_MCP2515_IRQ), + .chip_select = 3, + .platform_data = &mcp251x_config, + .mode = SPI_MODE_0, + }, +#endif // CONFIG_CAN_MCP251X +}; + +static int mx51_vmx_spi_cs[] = { + VMX51_ECSPI1_CS0, + VMX51_ECSPI1_CS1, + VMX51_TSC2046_CS, + VMX51_MCP2515_CS, +}; + +static struct spi_imx_master mx51_vmx_spi_pdata = { + .chipselect = mx51_vmx_spi_cs, + .num_chipselect = ARRAY_SIZE(mx51_vmx_spi_cs), +}; + +static int sdhc_write_protect(struct device *dev) +{ + int rc = 0; + + if (to_platform_device(dev)->id == 0) + ; // WP pin not available + else + rc = gpio_get_value(VMX51_SD2_WP); + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + unsigned int rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(VMX51_SD1_CD); + else + rc = gpio_get_value(VMX51_SD2_CD); + + return rc; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28 | MMC_VDD_28_29 \ + | MMC_VDD_29_30 | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 52000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28 | MMC_VDD_28_29 \ + | MMC_VDD_29_30 | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static int mxc_sgtl5000_amp_enable(int enable) +{ + return 0; +} + +static int mxc_sgtl5000_clock_enable(int enable) +{ + return 0; +} + +static int headphone_det_status(void) +{ + return 0; +} + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .clock_enable = mxc_sgtl5000_clock_enable, + .sysclk = 12288000, +}; + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx51(); +} + +__setup("w1", w1_setup); + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + char *str; + struct tag *t; + struct tag *mem_tag = 0; + int total_mem = 0; + int left_mem = 0; + int gpu_mem = SZ_16M; + int fb_mem = SZ_16M; + + mxc_set_cpu_type(MXC_CPU_MX51); + if (!system_rev) + mxc_set_system_rev(0x51, CHIP_REV_3_0); + + get_cpu_wp = mx51_vmx_get_cpu_wp; + set_num_cpu_wp = mx51_vmx_set_num_cpu_wp; + get_dvfs_core_wp = mx51_vmx_get_dvfs_core_table; + num_cpu_wp = ARRAY_SIZE(cpu_wp_auto); + + for_each_tag(mem_tag, tags) { + if (mem_tag->hdr.tag == ATAG_MEM) { + total_mem = mem_tag->u.mem.size; + break; + } + } + + for_each_tag(t, tags) { + if (t->hdr.tag == ATAG_CMDLINE) { + str = t->u.cmdline.cmdline; + str = strstr(str, "mem="); + if (str != NULL) { + str += 4; + left_mem = memparse(str, &str); + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_nommu"); + if (str != NULL) + gpu_data.enable_mmu = 0; + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_memory="); + if (str != NULL) { + str += 11; + gpu_mem = memparse(str, &str); + } + + break; + } + } + + if (gpu_data.enable_mmu) + gpu_mem = 0; + + if (left_mem == 0 || left_mem > total_mem) + left_mem = total_mem - gpu_mem - fb_mem; + + if (mem_tag) { + fb_mem = total_mem - left_mem - gpu_mem; + if (fb_mem < 0) { + gpu_mem = total_mem - left_mem; + fb_mem = 0; + } + mem_tag->u.mem.size = left_mem; + + /*reserve memory for gpu*/ + if (!gpu_data.enable_mmu) { + gpu_device.resource[5].start = + mem_tag->u.mem.start + left_mem; + gpu_device.resource[5].end = + gpu_device.resource[5].start + gpu_mem - 1; + } +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) + if (fb_mem) { + mxcfb_resources[0].start = + gpu_data.enable_mmu ? + mem_tag->u.mem.start + left_mem : + gpu_device.resource[5].end + 1; + mxcfb_resources[0].end = + mxcfb_resources[0].start + fb_mem - 1; + } else { + mxcfb_resources[0].start = 0; + mxcfb_resources[0].end = 0; + } +#endif + } +} + +static void mxc_fix_reset(void) +{ + /* Fix gpio configuration */ + gpio_set_value(VMX51_OSC_EN, 0); +} + +#define PWGT1SPIEN (1<<15) +#define PWGT2SPIEN (1<<16) +#define USEROFFSPI (1<<3) + +static void mxc_power_off(void) +{ + /* We can do power down one of two ways: + Set the power gating + Set USEROFFSPI */ + + /* Set the power gate bits to power down */ + pmic_write_reg(REG_POWER_MISC, (PWGT1SPIEN|PWGT2SPIEN), + (PWGT1SPIEN|PWGT2SPIEN)); +} + +/*! + * Power Key interrupt handler. + */ +static irqreturn_t power_key_int(int irq, void *dev_id) +{ + pwrkey_callback cb = (pwrkey_callback)dev_id; + + cb((void *)1); + + if (gpio_get_value(VMX51_PWR_BTN)) + set_irq_type(irq, IRQF_TRIGGER_FALLING); + else + set_irq_type(irq, IRQF_TRIGGER_RISING); + + return 0; +} + +/*! + * Power Key initialization. + */ +static void mxc_register_powerkey(pwrkey_callback pk_cb) +{ + /* Set power key as wakeup resource */ + int irq, ret; + irq = gpio_to_irq(VMX51_PWR_BTN); + + if (gpio_get_value(VMX51_PWR_BTN)) + set_irq_type(irq, IRQF_TRIGGER_FALLING); + else + set_irq_type(irq, IRQF_TRIGGER_RISING); + + ret = request_irq(irq, power_key_int, 0, "power_key", pk_cb); + if (ret) + pr_info("register on-off key interrupt failed\n"); + else + enable_irq_wake(irq); +} + +static int mxc_pwrkey_getstatus(int id) +{ + return gpio_get_value(VMX51_PWR_BTN); +} + +static struct power_key_platform_data pwrkey_data = { + .key_value = KEY_F4, + .register_pwrkey = mxc_register_powerkey, + .get_key_status = mxc_pwrkey_getstatus, +}; + +#if defined(CONFIG_USB_EHCI_MXC) || defined(CONFIG_USB_EHCI_MXC_MODULE) +static int otg_mode_host; + +static int __init vmx51_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", vmx51_otg_mode); + +/* USB_CTRL_1 */ +#define MX51_USB_CTRL_1_OFFSET 0x10 +#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) + +#define MX51_USB_PLLDIV_12_MHZ 0x00 +#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 +#define MX51_USB_PLL_DIV_24_MHZ 0x02 + +/* This function is board specific as the bit mask for the plldiv will also +be different for other Freescale SoCs, thus a common bitmask is not +possible and cannot get place in /plat-mxc/ehci.c.*/ +static int initialize_otg_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + u32 usbother_base; + + usb_base = ioremap(OTG_BASE_ADDR, SZ_4K); + usbother_base = (u32) usb_base + MX5_USBOTHER_REGS_OFFSET; + + /* Set the PHY clock to 19.2MHz */ + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; + v |= MX51_USB_PLL_DIV_19_2_MHZ; + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + iounmap(usb_base); + return 0; +} + +static int initialize_usbh1_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + u32 usbother_base; + + usb_base = ioremap(OTG_BASE_ADDR, SZ_4K); + usbother_base = (u32) usb_base + MX5_USBOTHER_REGS_OFFSET; + + /* The clock for the USBH1 ULPI port will come externally from the PHY. */ + v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); + __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); + iounmap(usb_base); + return 0; +} + +static struct mxc_usbh_platform_data dr_utmi_config = { + .init = initialize_otg_port, + .portsc = MXC_EHCI_UTMI_16BIT, + .flags = MXC_EHCI_INTERNAL_PHY, +}; + +static struct fsl_usb2_platform_data usb_pdata = { + .platform_init = initialize_otg_port, + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, +}; + +static struct mxc_usbh_platform_data usbh1_config = { + .init = initialize_usbh1_port, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), +}; +#endif // CONFIG_USB_EHCI_MXC + +#if defined(CONFIG_USB_EHCI_ARC) || defined(CONFIG_USB_EHCI_ARC_MODULE) +static void vmx51_gpio_usbotg_vbus_active(void) +{ + gpio_set_value(VMX51_USB0_PEN, 1); +} + +static void vmx51_gpio_usbotg_vbus_inactive(void) +{ + gpio_set_value(VMX51_USB0_PEN, 0); +} + +static void vmx51_gpio_usbotg_driver_vbus(bool on) +{ + if (on) + vmx51_gpio_usbotg_vbus_active(); + else + vmx51_gpio_usbotg_vbus_inactive(); +} +#endif // CONFIG_USB_EHCI_ARC + +static void __init mx51_vmx_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(vmx51_pads, ARRAY_SIZE(vmx51_pads)); + + /* Peripheral reset - Assert */ + gpio_request(VMX51_PER_RST, "per-rst"); + gpio_direction_output(VMX51_PER_RST, 0); + gpio_set_value(VMX51_PER_RST, 0); + + /* USBH1 PHY reset - Assert */ + gpio_request(VMX51_USBH1_PHY_RST, "usbh1-phy-reset"); + gpio_direction_output(VMX51_USBH1_PHY_RST, 0); + gpio_set_value(VMX51_USBH1_PHY_RST, 0); + + /* OSC */ + gpio_request(VMX51_OSC_EN, "26m-osc-en"); + gpio_direction_output(VMX51_OSC_EN, 1); + gpio_set_value(VMX51_OSC_EN, 1); + + /* PMIC */ + gpio_request(VMX51_PMIC_INT, "pmic-int"); + gpio_request(VMX51_PMIC_WDI, "pmix-wdi"); + gpio_direction_input(VMX51_PMIC_INT); + gpio_direction_output(VMX51_PMIC_WDI, 1); + gpio_set_value(VMX51_PMIC_WDI, 1); + gpio_free(VMX51_PMIC_WDI); // ? + + /* SD1 */ + gpio_request(VMX51_SD1_CD, "sdhc1-detect"); +// gpio_request(VMX51_SD1_WP, "sdhc1-wp"); + gpio_direction_input(VMX51_SD1_CD); +// gpio_direction_input(VMX51_SD1_WP); + + /* SD2 */ + gpio_request(VMX51_SD2_CD, "sdhc2-detect"); + gpio_request(VMX51_SD2_WP, "sdhc2-wp"); + gpio_direction_input(VMX51_SD2_CD); + gpio_direction_input(VMX51_SD2_WP); + + /* SPI */ + gpio_request(VMX51_ECSPI1_CS0, "ecspi-cs0"); + gpio_request(VMX51_ECSPI1_CS1, "ecspi-cs1"); + gpio_direction_output(VMX51_ECSPI1_CS0, 1); + gpio_direction_output(VMX51_ECSPI1_CS1, 1); + gpio_free(VMX51_ECSPI1_CS0); + gpio_free(VMX51_ECSPI1_CS1); + + /* FM fix IO level */ + gpio_request(VMX51_FM_IRQ, "fm-reset"); + gpio_direction_output(VMX51_FM_IRQ, 0); + gpio_set_value(VMX51_FM_IRQ, 0); + gpio_free(VMX51_FM_IRQ); + + /* Touch */ + gpio_request(VMX51_TSC2046_IRQ, "touch-irq"); + gpio_request(VMX51_TSC2046_CS, "touch-cs"); + gpio_direction_input(VMX51_TSC2046_IRQ); + gpio_direction_output(VMX51_TSC2046_CS, 1); + gpio_free(VMX51_TSC2046_CS); + + /* Can */ + gpio_request(VMX51_MCP2515_IRQ, "can-irq"); + gpio_request(VMX51_MCP2515_CS, "can-cs"); + gpio_direction_input(VMX51_MCP2515_IRQ); + gpio_direction_output(VMX51_MCP2515_CS, 1); + gpio_free(VMX51_MCP2515_IRQ); + gpio_free(VMX51_MCP2515_CS); + + /* Assert USB0 VBUS Disable */ + gpio_request(VMX51_USB0_PEN, "usb0-vbus-en"); + gpio_direction_output(VMX51_USB0_PEN, 0); + gpio_set_value(VMX51_USB0_PEN, 0); + + /* Reset USBH1 HUB */ +// gpio_request(??? , "hub-rst"); +// gpio_direction_output(???, 0); +// gpio_set_value(???, 0); +// msleep(1); +// gpio_set_value(???, 1); + + /* LED */ + gpio_request(VMX51_LED_RED, "led0"); + gpio_request(VMX51_LED_ORANGE, "led1"); + gpio_direction_output(VMX51_LED_RED, 0); + gpio_direction_output(VMX51_LED_ORANGE, 0); + gpio_free(VMX51_LED_RED); + gpio_free(VMX51_LED_ORANGE); + + /* SCR */ + gpio_request(VMX51_SCR_RST, "scr-rst"); + gpio_direction_output(VMX51_SCR_RST, 1); + gpio_set_value(VMX51_SCR_RST, 0); + gpio_free(VMX51_SCR_RST); + + /* reset FEC PHY */ + gpio_request(VMX51_FEC_RST, "fec-phy-reset"); + gpio_direction_output(VMX51_FEC_RST, 0); + msleep(10); + gpio_set_value(VMX51_FEC_RST, 1); + + /* DISP1 */ + gpio_request(VMX51_LCD_PSAVE, "disp1-psave"); + gpio_direction_output(VMX51_LCD_PSAVE, 1); + gpio_set_value(VMX51_LCD_PSAVE, 1); + + /* power key */ + gpio_request(VMX51_PWR_BTN, "power-key"); + gpio_direction_input(VMX51_PWR_BTN); + + /* USBH1 PHY reset - De-assert */ + gpio_set_value(VMX51_USBH1_PHY_RST, 1); + + /* Peripheral reset - De-assert */ + gpio_set_value(VMX51_PER_RST, 1); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + struct clk * tmp_clk; + + mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1"); + mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2"); + + tmp_clk = clk_get(NULL, "ckih"); + clk_disable(tmp_clk); + tmp_clk = clk_get(NULL, "ckih2"); + clk_disable(tmp_clk); + + /* SD card detect irqs */ + mxcsdhc1_device.resource[2].start = gpio_to_irq(VMX51_SD1_CD); + mxcsdhc1_device.resource[2].end = gpio_to_irq(VMX51_SD1_CD); + mxcsdhc2_device.resource[2].start = gpio_to_irq(VMX51_SD2_CD); + mxcsdhc2_device.resource[2].end = gpio_to_irq(VMX51_SD2_CD); + + mxc_cpu_common_init(); + mx51_vmx_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mx51_vmx_spi_pdata); +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) + mxc_register_device(&mxcuart_devices[0], &uart1_pdata); + mxc_register_device(&mxcuart_devices[1], &uart2_pdata); + mxc_register_device(&mxcuart_devices[2], &uart3_pdata); +#endif // CONFIG_SERIAL_IMX + mxc_register_device(&mxci2c_devices[0], &mxci2c1_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c2_data); + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + mxc_register_device(&mxc_rtc_device, NULL); + if (enable_w1) + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); + mxc_register_device(&mxcvpu_device, &mxc_vpu_data); + mxc_register_device(&gpu_device, &gpu_data); + mxc_register_device(&mxcscc_device, NULL); + + mxc_register_device(&mx51_lpmode_device, NULL); + mxc_register_device(&busfreq_device, &bus_freq_data); + mxc_register_device(&sdram_autogating_device, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); + + mxc_register_device(&mxc_iim_device, &iim_data); + mxc_register_device(&mxc_pwm1_device, NULL); + mxc_register_device(&mxc_pwm1_backlight_device, &mxc_pwm_backlight_data); + mxc_register_device(&mxc_keypad_device, &keypad_plat_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&mxc_ssi3_device, NULL); + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mxc_register_device(&mxc_fec_device, NULL); + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); + mxc_register_device(&mxc_powerkey_device, &pwrkey_data); + platform_device_register(&vmx_led_device); + +/* USB Drivers */ +#if defined(CONFIG_USB_EHCI_MXC) || defined(CONFIG_USB_EHCI_MXC_MODULE) // imx driver +/* CONFIG_USB_GADGET_FSL_USB2 */ + if (otg_mode_host) { + gpio_set_value(VMX51_USB0_PEN, 1); + mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + } else { + gpio_set_value(VMX51_USB0_PEN, 0); + mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); + } + + mxc_register_device(&mxc_usbh1_device, &usbh1_config); +#elif defined(CONFIG_USB_EHCI_ARC) || defined(CONFIG_USB_EHCI_ARC_MODULE) // fsl driver +/* CONFIG_USB_GADGET_ARC */ + mx5_set_otghost_vbus_func(vmx51_gpio_usbotg_driver_vbus); + mx5_usb_dr_init(); + +// mx5_set_host1_vbus_func(vmx51_gpio_host1_driver_vbus); + mx5_usbh1_init(); +#endif + +/* NAND Drivers */ +#if defined(CONFIG_MTD_NAND_IMX_NFC) || defined(CONFIG_MTD_NAND_IMX_NFC_MODULE) // imx driver + mxc_register_device(&imx_nfc_device, &imx_nfc_platform_data); +#elif defined(CONFIG_MTD_NAND_MXC_V3) || defined(CONFIG_MTD_NAND_MXC_V3_MODULE) // fsl driver + mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data); +#endif + + mx51_vmx_init_mc13892(); + + /* Register Devices */ + spi_register_board_info(mxc_ecspi1_board_info, ARRAY_SIZE(mxc_ecspi1_board_info)); + i2c_register_board_info(0, mxc_i2c1_board_info, ARRAY_SIZE(mxc_i2c1_board_info)); + i2c_register_board_info(1, mxc_i2c2_board_info, ARRAY_SIZE(mxc_i2c2_board_info)); + + mxc_plat_reset = mxc_fix_reset; + pm_power_off = mxc_power_off; +} + +static void __init vmx51_timer_init(void) +{ + struct clk *uart_clk; + + mx51_clocks_init(32768, 24000000, 26000000, 0); + + uart_clk = clk_get_sys("mxcintuart.0", NULL); + early_console_setup(UART1_BASE_ADDR, uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = vmx51_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_VMX51 data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(VMX51, "Voipac VMX51 Board") + /* Maintainer: Voipac a.s. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx51_vmx_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_vmx_pmic_mc13892.c index e69de29..b559092 100644 --- a/arch/arm/mach-mx5/mx51_vmx_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx51_vmx_pmic_mc13892.c @@ -0,0 +1,480 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011 Voipac a.s., All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// GPIO settings +#define VMX51_PMIC_INT (0*32 + 3) /* GPIO_1_3 */ + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +/* Standby pin polarity */ +#define STANDBYSECINV_LSH 11 +#define STANDBYSECINV_WID 1 +/* Coin cell charger enable */ +#define COINCHEN_LSH 23 +#define COINCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* regulator standby mask */ +#define GEN1_STBY_MASK (1 << 1) +#define IOHI_STBY_MASK (1 << 4) +#define DIG_STBY_MASK (1 << 10) +#define GEN2_STBY_MASK (1 << 13) +#define PLL_STBY_MASK (1 << 16) +#define USB2_STBY_MASK (1 << 19) + +#define GEN3_STBY_MASK (1 << 1) +#define CAM_STBY_MASK (1 << 7) +#define VIDEO_STBY_MASK (1 << 13) +#define AUDIO_STBY_MASK (1 << 16) +#define SD_STBY_MASK (1 << 19) + +#define GPO1_STBY_MASK (1 << 7) +#define GPO2_STBY_MASK (1 << 9) +#define GPO3_STBY_MASK (1 << 11) +#define GPO4_STBY_MASK (1 << 13) + +#define REG_MODE_0_STBY_MASK \ + (GEN1_STBY_MASK | IOHI_STBY_MASK |\ + DIG_STBY_MASK | PLL_STBY_MASK | USB2_STBY_MASK) + +#define REG_MODE_1_STBY_MASK \ + (0) + +#define REG_POWER_MISC_STBY_MASK \ + (GPO1_STBY_MASK | GPO2_STBY_MASK |\ + GPO3_STBY_MASK) + +/* regulator enable mask */ +#define GEN1_EN_MASK (1 << 0) +#define IOHI_EN_MASK (1 << 3) +#define DIG_EN_MASK (1 << 9) +#define GEN2_EN_MASK (1 << 12) +#define PLL_EN_MASK (1 << 15) +#define USB2_EN_MASK (1 << 18) + +#define GEN3_EN_MASK (1 << 0) +#define CAM_EN_MASK (1 << 6) +#define VIDEO_EN_MASK (1 << 12) +#define AUDIO_EN_MASK (1 << 15) +#define SD_EN_MASK (1 << 18) + +#define GPO1_EN_MASK (1 << 6) +#define GPO2_EN_MASK (1 << 8) +#define GPO3_EN_MASK (1 << 10) +#define GPO4_EN_MASK (1 << 12) +#define PWGT1SPIEN (1 << 15) +#define PWGT2SPIEN (1 << 16) + +// VIOHI must stay enabled or GPO will be turned off +#define REG_MODE_0_DISABLE_MASK \ + (GEN2_EN_MASK | GEN2_STBY_MASK) + +#define REG_MODE_1_DISABLE_MASK \ + (GEN3_EN_MASK | GEN3_STBY_MASK |\ + CAM_EN_MASK | CAM_STBY_MASK |\ + VIDEO_EN_MASK | VIDEO_STBY_MASK |\ + AUDIO_EN_MASK | AUDIO_STBY_MASK |\ + SD_EN_MASK | SD_STBY_MASK) + +#define REG_POWER_MISC_DISABLE_MASK \ + (GPO4_EN_MASK | GPO4_STBY_MASK |\ + PWGT1SPIEN | PWGT2SPIEN) + +/* switch mode setting */ +#define SW1MODE_LSB 0 +#define SW2MODE_LSB 10 +#define SW3MODE_LSB 0 +#define SW4MODE_LSB 8 + +#define SWMODE_MASK 0xF +#define SWMODE_AUTO 0x8 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vddgp", + } +}; + +static struct regulator_consumer_supply sw2_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +static struct regulator_consumer_supply sw3_consumers[] = { + { + .supply = "cpu_vdda", + } +}; + +static struct regulator_consumer_supply sw4_consumers[] = { + { .supply = "cpu_nvcc_per3",}, + { .supply = "cpu_nvcc_per5",}, + { .supply = "cpu_nvcc_per8",}, + { .supply = "cpu_nvcc_per9",}, + { .supply = "cpu_nvcc_per10",}, + { .supply = "cpu_nvcc_per11",}, + { .supply = "cpu_nvcc_per12",}, + { .supply = "cpu_nvcc_per13",}, + { .supply = "cpu_nvcc_per14",}, + { .supply = "cpu_nvcc_per15",}, + { .supply = "cpu_nvcc_per17",}, + { .supply = "cpu_nvcc_i2c",}, +}; + +static struct regulator_consumer_supply vgen1_consumers[] = { + { + .supply = "vfec", + } +}; + +static struct regulator_consumer_supply vusb2_consumers[] = { + { .supply = "cpu_nvcc_usbphy",}, + { .supply = "cpu_nvcc_osc",} +}; + +static struct regulator_consumer_supply vdig_consumers[] = { + { + .supply = "cpu_vdd_dig_pll", + }, +}; + +static struct regulator_consumer_supply vpll_consumers[] = { + { + .supply = "cpu_vdd_ana_pll", + }, +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw2_consumers), + .consumer_supplies = sw2_consumers, +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(sw3_consumers), + .consumer_supplies = sw3_consumers, +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(sw4_consumers), + .consumer_supplies = sw4_consumers, +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vdig_consumers), + .consumer_supplies = vdig_consumers, +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vpll_consumers), + .consumer_supplies = vpll_consumers, +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vusb2_consumers), + .consumer_supplies = vusb2_consumers, +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen1_consumers), + .consumer_supplies = vgen1_consumers, +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 0, + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + } +}; + +/*! + * the event handler for power on event + */ +//static void power_on_evt_handler(void) +//{ +// pr_info("pwr on event1 is received \n"); +//} + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value, register_mask; +// pmic_event_callback_t power_key_event; + printk("Initializing regulators for VMX51.\n"); + + if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) + sw2_init.constraints.state_mem.uV = 1100000; + else if (mxc_cpu_is_rev(CHIP_REV_2_0) == 1) { + sw2_init.constraints.state_mem.uV = 1250000; + sw1_init.constraints.state_mem.uV = 1000000; + } + + /* subscribe PWRON1 event to enable ON_OFF key */ +// power_key_event.param = NULL; +// power_key_event.func = (void *)power_on_evt_handler; +// pmic_event_subscribe(EVENT_PWRONI, power_key_event); + + // disable not used regulators & enable standby controll for all active regulators + pmic_read_reg(REG_MODE_0, &value, 0xffffff); + value = (value & ~REG_MODE_0_DISABLE_MASK) | REG_MODE_0_STBY_MASK; + pmic_write_reg(REG_MODE_0, value, 0xffffff); + + pmic_read_reg(REG_MODE_1, &value, 0xffffff); + value = (value & ~REG_MODE_1_DISABLE_MASK) | REG_MODE_1_STBY_MASK; + pmic_write_reg(REG_MODE_1, value, 0xffffff); + + pmic_read_reg(REG_POWER_MISC, &value, 0xffffff); + value = (value & ~REG_POWER_MISC_DISABLE_MASK) | REG_POWER_MISC_STBY_MASK; + pmic_write_reg(REG_POWER_MISC, value, 0xffffff); + + pmic_read_reg(REG_SW_5, &value, 0xffffff); // DISABLE SWBST + value = (value & ~(1<<20)) | 0x0; + pmic_write_reg(REG_SW_5, value, 0xffffff); + + // enable switch audo mode + pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff); + // only for mc13892 2.0A + if ((value & 0x0000FFFF) == 0x45d0) { // MASU FIXME force PFM mode + pmic_read_reg(REG_SW_4, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW1MODE_LSB) | + (SWMODE_MASK << SW2MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW1MODE_LSB) | + (SWMODE_AUTO << SW2MODE_LSB); + pmic_write_reg(REG_SW_4, value, 0xffffff); + + pmic_read_reg(REG_SW_5, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW3MODE_LSB) | + (SWMODE_MASK << SW4MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW3MODE_LSB) | + (SWMODE_AUTO << SW4MODE_LSB); + pmic_write_reg(REG_SW_5, value, 0xffffff); + } + + /* Set the STANDBYSECINV bit, so that STANDBY pin is // MASU FIXME + * interpreted as active low. + */ + value = BITFVAL(STANDBYSECINV, 1); + register_mask = BITFMASK(STANDBYSECINV); + pmic_write_reg(REG_POWER_CTL2, value, register_mask); + + /* Enable/Disable coin cell charger since the cell is not rechargeable */ +#if defined CONFIG_MXC_MC13892_BACKUP_BATT + value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); +#else + value = BITFVAL(COINCHEN, 0) | BITFVAL(VCOIN, VCOIN_3_0V); +#endif // CONFIG_MXC_MC13892_BACKUP_BATT + register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct i2c_board_info __initdata mc13892_i2c_device = { + I2C_BOARD_INFO("mc13892", 0x08), + .irq = gpio_to_irq(VMX51_PMIC_INT), + .platform_data = &mc13892_plat, +}; + +int __init mx51_vmx_init_mc13892(void) +{ + return i2c_register_board_info(0, &mc13892_i2c_device, 1); +} diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 101105e..255e45e 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -704,6 +704,12 @@ config CPU_CACHE_ROUND_ROBIN Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. +config ARM_ENABLE_L2 + bool "Enable L2 cache" + depends on CPU_V7 && CPU_CP15 + help + This options enables ARMv7 L2 cache + config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7aaf88a..1a7cffa 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -209,6 +209,11 @@ __v7_setup: and r6, r0, #0x0000000f @ revision orr r0, r6, r5, lsr #20-4 @ combine variant and revision +#ifdef CONFIG_ARM_ENABLE_L2 + mrc p15, 0, r10, c1, c0, 1 @ R0 = auxiliary control reg + orr r10, r10, #0x2 @ Enable L2 cache + mcr p15, 0, r10, c1, c0, 1 @ Update aux control reg +#endif #ifdef CONFIG_ARM_ERRATA_430973 teq r5, #0x00100000 @ only present in r1p* mrceq p15, 0, r10, c1, c0, 1 @ read aux control register diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 2a86461..d400cbc 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -217,17 +217,17 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) switch (port) { case 0: /* OTG port */ - usbotg_base = usb_base + MXC_OTG_OFFSET; + usbotg_base = (u32) usb_base + MXC_OTG_OFFSET; break; case 1: /* Host 1 port */ - usbotg_base = usb_base + MXC_H1_OFFSET; + usbotg_base = (u32) usb_base + MXC_H1_OFFSET; break; default: printk(KERN_ERR"%s no such port %d\n", __func__, port); ret = -ENOENT; goto error; } - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + usbother_base = (u32) usb_base + MX5_USBOTHER_REGS_OFFSET; switch (port) { case 0: /*OTG port */ diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index a89e874..4185646 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -68,4 +68,7 @@ static inline int mx50_revision(void) {return 0; } static inline int mx51_revision(void) {return 0; } static inline int mx53_revision(void) {return 0; } #endif + +extern void (*mxc_plat_reset)(void); + #endif diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index a5a8df4..5a4b7b7 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -49,7 +49,7 @@ #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include +#include #define UART_PADDR MX51_UART1_BASE_ADDR #define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) #endif diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 4106de8..0acb2f0 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -52,6 +52,7 @@ #ifdef CONFIG_ARCH_MX5 #include +#include #endif #ifdef CONFIG_ARCH_MX3 diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 7cf2775..3b812b9 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -38,6 +38,8 @@ PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \ PAD_CTL_SRE_FAST | PAD_CTL_DVS) +#define MX51_NAND_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + #define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) #define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) @@ -487,7 +489,8 @@ #define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) #define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) #define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0) +//#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0) +#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0) #define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) #define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) #define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) @@ -847,21 +850,21 @@ #define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 LED */ #define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 LED */ #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) /* vmx51 can irq */ #define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) /* vmx51 touch irq */ #define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -995,26 +998,26 @@ #define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL | PAD_CTL_PUS_100K_UP)) #define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL | PAD_CTL_PUS_100K_UP)) #define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL | PAD_CTL_PUS_100K_UP)) #define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)) #define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) @@ -1025,14 +1028,14 @@ #define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2 | PAD_CTL_DVS)) #define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2 | PAD_CTL_DVS)) #define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -1040,7 +1043,7 @@ #define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) #define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DSE_HIGH)) #define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) @@ -1084,7 +1087,7 @@ #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL_PULL | PAD_CTL_PUS_100K_UP)) +#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL_PULL | PAD_CTL_ODE | PAD_CTL_DVS)) /* vmx51 gpio main clk + usb clk enable */ #define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -1093,22 +1096,22 @@ #define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL | PAD_CTL_DVS)) +#define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_PAD_CTRL_9)) /* vmx51 sd2 cd */ #define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL | PAD_CTL_DVS)) +#define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_PAD_CTRL_9)) /* vmx51 sd1 cd */ #define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL | PAD_CTL_DVS)) #define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) #define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL | PAD_CTL_PUS_100K_UP | PAD_CTL_DVS)) /* vmx51 fec rst */ #define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -1123,41 +1126,41 @@ #define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(MX51_NAND_PAD_CTRL)) #define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -1320,33 +1323,33 @@ #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) #define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_PAD_CTRL_9)) /* vmx51 sd2 wp */ #define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 nc */ #define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 peripheral reset */ #define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 ssi1 int */ #define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 fm irq */ #define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 ecspi can cs */ #define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 ecspi touch cs */ #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 smard card reader rst */ #define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 psave vga dvi */ #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -1512,10 +1515,10 @@ #define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) #define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHC_PAD_CTRL)) #define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) +#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) /* vmx51 msp430 i2c int */ #define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) #define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) +#define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(MX51_PAD_CTRL_7 | PAD_CTL_PUS_100K_UP)) /* GPIO1 temporary PWR button */ #define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) #define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -1544,7 +1547,7 @@ #define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) #define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(MX51_UART3_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(MX51_UART3_PAD_CTRL | PAD_CTL_PUS_100K_DOWN)) /* vmx51 pmic int */ #define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) #define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -1552,27 +1555,27 @@ #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) +#define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) /* vmx51 pmic vdi */ #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(MX51_PAD_CTRL_7)) +#define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(MX51_PAD_CTRL_9)) /* vmx51 usbh1 oc */ #define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) /* vmx51 usbh1 reset */ #define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) #define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(MX51_PAD_CTRL_6)) +#define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(MX51_PAD_CTRL_6)) /* vmx51 usbo pwr */ #define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) #define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(MX51_PAD_CTRL_9)) /* vmx51 usbo oc */ #define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 33fe6f8..f399954 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -26,6 +26,8 @@ void arch_idle(void); +void (*mxc_plat_reset)(void); + void arch_reset(char mode, const char *cmd); int mxs_reset_block(void __iomem *hwreg, int just_enable); diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index d3c46b1..0a363be 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -106,6 +106,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) uart_base = MX3X_UART2_BASE_ADDR; break; case MACH_TYPE_MX51_BABBAGE: + case MACH_TYPE_VMX51: uart_base = MX51_UART1_BASE_ADDR; break; case MACH_TYPE_MX53_EVK: diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 253429b..8070354 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -45,6 +45,10 @@ void arch_reset(char mode, const char *cmd) { unsigned int wcr_enable; + /* call the platform reset prepare function */ + if (mxc_plat_reset) + (mxc_plat_reset)(); + #ifdef CONFIG_ARCH_MXC91231 if (cpu_is_mxc91231()) { mxc91231_arch_reset(mode, cmd); diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 81e49a9..7c1924a 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -632,6 +632,7 @@ static const struct spi_device_id m25p_ids[] = { { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, + { "at25df081", INFO(0x1f4502, 0, 64 * 1024, 16, SECT_4K) }, { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, diff --git a/drivers/mtd/devices/mxc_m25p80.c b/drivers/mtd/devices/mxc_m25p80.c index 6ee10b8..0abf727 100644 --- a/drivers/mtd/devices/mxc_m25p80.c +++ b/drivers/mtd/devices/mxc_m25p80.c @@ -772,6 +772,7 @@ static const struct spi_device_id m25p_ids[] = { {"at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K)}, {"at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K)}, + {"at25df081", INFO(0x1f4502, 0, 64 * 1024, 16, SECT_4K)}, {"at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K)}, {"at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K)}, diff --git a/drivers/mtd/nand/imx_nfc.c b/drivers/mtd/nand/imx_nfc.c index 065ff33..e0ed2ca 100644 --- a/drivers/mtd/nand/imx_nfc.c +++ b/drivers/mtd/nand/imx_nfc.c @@ -24,6 +24,7 @@ #include #include #include +#include #define DRIVER_VERSION "1.0" @@ -6124,7 +6125,7 @@ static int mil_ecc_correct(struct mtd_info *mtd, * @buf: A pointer to the destination buffer. */ static int mil_ecc_read_page(struct mtd_info *mtd, - struct nand_chip *nand, uint8_t *buf) + struct nand_chip *nand, uint8_t *buf, int page) { int ecc_status; struct imx_nfc_data *this = nand->priv; @@ -6163,7 +6164,7 @@ static int mil_ecc_read_page(struct mtd_info *mtd, * @buf: A pointer to the destination buffer. */ static int mil_ecc_read_page_raw(struct mtd_info *mtd, - struct nand_chip *nand, uint8_t *buf) + struct nand_chip *nand, uint8_t *buf, int page) { struct imx_nfc_data *this = nand->priv; @@ -6664,24 +6665,24 @@ static int get_module_force_bytewise_copy(char *p, struct kernel_param *kp) /* Module attributes that appear in sysfs. */ -module_param_call(enable, set_module_enable, get_module_enable, 0, 0444); +module_param_call(enable, set_module_enable, get_module_enable, NULL, 0444); MODULE_PARM_DESC(enable, "enables/disables probing"); #ifdef EVENT_REPORTING module_param_call(report_events, - set_module_report_events, get_module_report_events, 0, 0644); + set_module_report_events, get_module_report_events, NULL, 0644); MODULE_PARM_DESC(report_events, "enables/disables event reporting"); -module_param_call(dump_events, set_module_dump_events, 0, 0, 0644); +module_param_call(dump_events, set_module_dump_events, NULL, NULL, 0644); MODULE_PARM_DESC(dump_events, "forces current event dump"); #endif module_param_call(interleave_override, set_module_interleave_override, - get_module_interleave_override, 0, 0444); + get_module_interleave_override, NULL, 0444); MODULE_PARM_DESC(interleave_override, "overrides interleaving choice"); module_param_call(force_bytewise_copy, set_module_force_bytewise_copy, - get_module_force_bytewise_copy, 0, 0644); + get_module_force_bytewise_copy, NULL, 0644); MODULE_PARM_DESC(force_bytewise_copy, "forces bytewise copy from/to NFC"); /** @@ -6779,8 +6780,8 @@ static ssize_t show_device_platform_info(struct device *dev, break; default: o += sprintf(buf+o, " Offset: %u (%u MiB)\n", - partition->offset, - partition->offset / (1024 * 1024)); + (unsigned int) partition->offset, + (unsigned int) (partition->offset / (1024 * 1024))); break; } @@ -6790,8 +6791,8 @@ static ssize_t show_device_platform_info(struct device *dev, "MTDPART_SIZ_FULL\n"); } else { o += sprintf(buf+o, " Size : %u (%u MiB)\n", - partition->size, - partition->size / (1024 * 1024)); + (unsigned int) partition->size, + (unsigned int) (partition->size / (1024 * 1024))); } } @@ -6974,7 +6975,7 @@ static ssize_t show_device_mtd_nand_info(struct device *dev, , nand->options, nand->numchips, - nand->chipsize, + (long unsigned int) nand->chipsize, nand->subpagesize, nand->page_shift, nand->pagemask, @@ -7057,7 +7058,7 @@ static ssize_t show_device_mtd_info(struct device *dev, "Name : %s\n" "Type : %u\n" "Flags : 0x%08x\n" - "Size in Bytes : %u\n" + "Size in Bytes : %lu\n" "Erase Region Count : %d\n" "Erase Size in Bytes: %u\n" "Write Size in Bytes: %u\n" @@ -7070,7 +7071,7 @@ static ssize_t show_device_mtd_info(struct device *dev, mtd->name, mtd->type, mtd->flags, - mtd->size, + (long unsigned int) mtd->size, mtd->numeraseregions, mtd->erasesize, mtd->writesize, @@ -7627,7 +7628,7 @@ static int acquire_resources(struct imx_nfc_data *this) this->interrupt = r->start; error = request_irq(this->interrupt, - nfc_util_isr, 0, this->dev->bus_id, this); + nfc_util_isr, 0, "imx_nfc", this); if (error) { dev_err(dev, "Can't own interrupt %d\n", this->interrupt); diff --git a/drivers/mtd/nand/nand_device_info.c b/drivers/mtd/nand/nand_device_info.c index 6a23810..e03a437 100644 --- a/drivers/mtd/nand/nand_device_info.c +++ b/drivers/mtd/nand/nand_device_info.c @@ -136,6 +136,25 @@ static struct nand_device_info nand_device_info_table_type_2[] __initdata = { }, { .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xa1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F1G08", + }, + { + .end_of_table = false, .manufacturer_code = 0x20, .device_code = 0xda, .cell_technology = NAND_DEVICE_CELL_TECH_SLC, @@ -916,6 +935,25 @@ static struct nand_device_info nand_device_info_table_type_7[] __initdata = { { .end_of_table = false, .manufacturer_code = 0x2c, + .device_code = 0xa3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F8G08ADBDA", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, .device_code = 0xd3, .cell_technology = NAND_DEVICE_CELL_TECH_SLC, .chip_size_in_bytes = 1LL*SZ_1G, @@ -935,6 +973,25 @@ static struct nand_device_info nand_device_info_table_type_7[] __initdata = { { .end_of_table = false, .manufacturer_code = 0x2c, + .device_code = 0xac, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F4G08ABB", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, .device_code = 0xdc, .cell_technology = NAND_DEVICE_CELL_TECH_SLC, .chip_size_in_bytes = 512LL*SZ_1M, diff --git a/drivers/mxc/pmic/core/mc13892.c b/drivers/mxc/pmic/core/mc13892.c index 260d3e2..c6fac86 100644 --- a/drivers/mxc/pmic/core/mc13892.c +++ b/drivers/mxc/pmic/core/mc13892.c @@ -61,7 +61,7 @@ EXPORT_SYMBOL(mc13892_alloc_data); int mc13892_init_registers(void) { CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF)); - CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF)); + CHECK_ERROR(pmic_write(REG_INT_MASK1, 0xFFFFFF)); CHECK_ERROR(pmic_write(REG_INT_STATUS0, 0xFFFFFF)); CHECK_ERROR(pmic_write(REG_INT_STATUS1, 0xFFFFFF)); /* disable auto charge */ diff --git a/drivers/mxc/pmic/mc13892/Kconfig b/drivers/mxc/pmic/mc13892/Kconfig index 930e06a..219538b 100644 --- a/drivers/mxc/pmic/mc13892/Kconfig +++ b/drivers/mxc/pmic/mc13892/Kconfig @@ -18,6 +18,7 @@ config MXC_MC13892_RTC This is the MC13892 RTC module driver. This module provides kernel API for RTC part of MC13892. If you want MC13892 RTC support, you should say Y here + config MXC_MC13892_LIGHT tristate "MC13892 Light and Backlight support" depends on MXC_PMIC_MC13892 @@ -25,6 +26,7 @@ config MXC_MC13892_LIGHT This is the MC13892 Light module driver. This module provides kernel API for led and backlight control part of MC13892. If you want MC13892 Light support, you should say Y here + config MXC_MC13892_BATTERY tristate "MC13892 Battery API support" depends on MXC_PMIC_MC13892 @@ -32,6 +34,14 @@ config MXC_MC13892_BATTERY This is the MC13892 battery module driver. This module provides kernel API for battery control part of MC13892. If you want MC13892 battery support, you should say Y here + +config MXC_MC13892_BACKUP_BATT + tristate "MC13892 Backup Battery charger enable" + depends on MXC_PMIC_MC13892 + ---help--- + This option enable the MC13892 coin battery charger. + If you want MC13892 coin battery to be charged, you should say Y here + config MXC_MC13892_CONNECTIVITY tristate "MC13892 Connectivity API support" depends on MXC_PMIC_MC13892 @@ -39,6 +49,7 @@ config MXC_MC13892_CONNECTIVITY This is the MC13892 connectivity module driver. This module provides kernel API for USB/RS232 connectivity control part of MC13892. If you want MC13892 connectivity support, you should say Y here + config MXC_MC13892_POWER tristate "MC13892 Power API support" depends on MXC_PMIC_MC13892 diff --git a/drivers/mxc/pmic/mc13892/pmic_battery.c b/drivers/mxc/pmic/mc13892/pmic_battery.c index 3e6cf7f..509d69b 100644 --- a/drivers/mxc/pmic/mc13892/pmic_battery.c +++ b/drivers/mxc/pmic/mc13892/pmic_battery.c @@ -33,16 +33,16 @@ #define BIT_CHG_VOL_LSH 0 #define BIT_CHG_VOL_WID 3 -#define BIT_CHG_CURR_LSH 3 -#define BIT_CHG_CURR_WID 4 +#define BIT_CHG_CURR_LSH 3 +#define BIT_CHG_CURR_WID 4 -#define BIT_CHG_PLIM_LSH 15 -#define BIT_CHG_PLIM_WID 2 +#define BIT_CHG_PLIM_LSH 15 +#define BIT_CHG_PLIM_WID 2 -#define BIT_CHG_DETS_LSH 6 -#define BIT_CHG_DETS_WID 1 -#define BIT_CHG_CURRS_LSH 11 -#define BIT_CHG_CURRS_WID 1 +#define BIT_CHG_DETS_LSH 6 +#define BIT_CHG_DETS_WID 1 +#define BIT_CHG_CURRS_LSH 11 +#define BIT_CHG_CURRS_WID 1 #define TRICKLE_CHG_EN_LSH 7 #define LOW_POWER_BOOT_ACK_LSH 8 @@ -131,6 +131,18 @@ static int pmic_set_chg_current(unsigned short curr) return 0; } +static int pmic_set_chg_voltage(unsigned short vout) +{ + unsigned int mask; + unsigned int value; + + value = BITFVAL(BIT_CHG_VOL, vout); + mask = BITFMASK(BIT_CHG_VOL); + CHECK_ERROR(pmic_write_reg(REG_CHARGE, value, mask)); + + return 0; +} + static int pmic_set_chg_misc(enum chg_setting type, unsigned short flag) { @@ -301,6 +313,17 @@ static int pmic_get_charger_coulomb(int *coulomb) static int pmic_restart_charging(void) { +/* + pmic_set_chg_voltage(0x3); + pmic_set_chg_current(0x8); + pmic_set_chg_misc(BAT_TH_CHECK_DIS, 1); + pmic_set_chg_misc(AUTO_CHG_DIS, 1); // 21 Default 0 FIXME (bootloader will handle it) +// pmic_set_chg_misc(TRICKLE_CHG_EN, 0); // disable new + pmic_set_chg_misc(PLIM_DIS, 1); // 17 + pmic_set_chg_misc(CYCLING_DIS, 1); // 22 new + pmic_set_chg_misc(VI_PROGRAM_EN, 1); // 23 + pmic_set_chg_misc(RESTART_CHG_STAT, 1); // 20 +*/ pmic_set_chg_misc(BAT_TH_CHECK_DIS, 1); pmic_set_chg_misc(AUTO_CHG_DIS, 0); pmic_set_chg_misc(VI_PROGRAM_EN, 1); @@ -455,9 +478,9 @@ static int mc13892_charger_update_status(struct mc13892_dev_info *di) cancel_delayed_work(&chg_work); chg_wa_timer = 0; pmic_stop_coulomb_counter(); + } } } - } return ret; } diff --git a/drivers/net/fec.c b/drivers/net/fec.c index 49a9890..e6d4a04 100644 --- a/drivers/net/fec.c +++ b/drivers/net/fec.c @@ -406,7 +406,10 @@ fec_enet_tx(struct net_device *dev) struct fec_enet_private *fep; struct fec_ptp_private *fpp; struct bufdesc *bdp; - unsigned short status; + unsigned short status = 0; +#if defined(CONFIG_ENHANCED_BD) + unsigned long estatus = 0; +#endif struct sk_buff *skb; fep = netdev_priv(dev); @@ -914,12 +917,12 @@ static void fec_enet_get_drvinfo(struct net_device *dev, strcpy(info->bus_info, dev_name(&dev->dev)); } -static int fec_enet_get_link(struct net_device *dev) +static u32 fec_enet_get_link(struct net_device *dev) { if (netif_running(dev)) return netif_carrier_ok(dev) ? 1 : 0; else - return -EINVAL; + return (u32)(-EINVAL); } static struct ethtool_ops fec_enet_ethtool_ops = { diff --git a/drivers/regulator/reg-mc13892.c b/drivers/regulator/reg-mc13892.c index e3c6ab3..3ffedb2 100644 --- a/drivers/regulator/reg-mc13892.c +++ b/drivers/regulator/reg-mc13892.c @@ -1935,6 +1935,7 @@ static struct platform_driver mc13892_regulator_driver = { .remove = mc13892_regulator_remove, .driver = { .name = "mc13892-regulatr", + /* o left out due to string length */ }, }; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 9987e37..5051468 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -545,17 +545,6 @@ config RTC_DRV_MSM6242 This driver can also be built as a module. If so, the module will be called rtc-msm6242. -config RTC_MXC - tristate "Freescale MXC Real Time Clock" - depends on ARCH_MXC - depends on RTC_CLASS - help - If you say yes here you get support for the Freescale MXC - RTC module. - - This driver can also be built as a module, if so, the module - will be called "rtc-mxc". - config RTC_DRV_BQ4802 tristate "TI BQ4802" help @@ -831,7 +820,11 @@ config RTC_MXC depends on ARCH_MXC depends on RTC_CLASS help - Support for Freescale RTC MXC + If you say yes here you get support for the Freescale MXC + RTC module. + + This driver can also be built as a module, if so, the module + will be called "rtc-mxc". config RTC_DRV_MXC_V2 tristate "Freescale MXC Secure Real Time Clock" diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index e58c086..f811aef 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -52,7 +52,6 @@ obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o -obj-$(CONFIG_RTC_MXC) += rtc-mxc.o obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o obj-$(CONFIG_RTC_DRV_MAX8925) += rtc-max8925.o obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o @@ -97,7 +96,7 @@ obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o obj-$(CONFIG_RTC_MXC) += rtc-mxc.o obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o -obj-$(CONFIG_RTC_MC13892) += rtc-mc13892.o +obj-$(CONFIG_RTC_MC13892) += rtc-mc13892.o obj-$(CONFIG_RTC_DRV_MXS) += rtc-mxs.o obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7248cb1..5aaafbe 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -143,10 +143,26 @@ config SPI_GPIO GPIO operations, you should be able to leverage that for better speed with a custom version of this driver; see the source code. +config SPI_IMX_VER_IMX1 + def_bool y if SOC_IMX1 + +config SPI_IMX_VER_0_0 + def_bool y if SOC_IMX21 || SOC_IMX27 + +config SPI_IMX_VER_0_4 + def_bool y if SOC_IMX31 + +config SPI_IMX_VER_0_7 + def_bool y if ARCH_MX25 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 + +config SPI_IMX_VER_2_3 + def_bool y if SOC_IMX51 || SOC_IMX53 + config SPI_IMX tristate "Freescale i.MX SPI controllers" depends on ARCH_MXC select SPI_BITBANG + default m if IMX_HAVE_PLATFORM_SPI_IMX help This enables using the Freescale i.MX SPI controllers in master mode. diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c index 7972e90..69d6dba 100644 --- a/drivers/spi/spi_imx.c +++ b/drivers/spi/spi_imx.c @@ -56,7 +56,27 @@ struct spi_imx_config { unsigned int speed_hz; unsigned int bpw; unsigned int mode; - int cs; + u8 cs; +}; + +enum spi_imx_devtype { + SPI_IMX_VER_IMX1, + SPI_IMX_VER_0_0, + SPI_IMX_VER_0_4, + SPI_IMX_VER_0_5, + SPI_IMX_VER_0_7, + SPI_IMX_VER_2_3, +}; + +struct spi_imx_data; + +struct spi_imx_devtype_data { + void (*intctrl)(struct spi_imx_data *, int); + int (*config)(struct spi_imx_data *, struct spi_imx_config *); + void (*trigger)(struct spi_imx_data *); + int (*rx_available)(struct spi_imx_data *); + void (*reset)(struct spi_imx_data *); + unsigned int fifosize; }; struct spi_imx_data { @@ -76,11 +96,7 @@ struct spi_imx_data { const void *tx_buf; unsigned int txfifo; /* number of words pushed in tx FIFO */ - /* SoC specific functions */ - void (*intctrl)(struct spi_imx_data *, int); - int (*config)(struct spi_imx_data *, struct spi_imx_config *); - void (*trigger)(struct spi_imx_data *); - int (*rx_available)(struct spi_imx_data *); + struct spi_imx_devtype_data devtype_data; }; #define MXC_SPI_BUF_RX(type) \ @@ -140,7 +156,7 @@ static unsigned int spi_imx_clkdiv_1(unsigned int fin, return max; } -/* MX1, MX31, MX35 */ +/* MX1, MX31, MX35, MX51 CSPI */ static unsigned int spi_imx_clkdiv_2(unsigned int fin, unsigned int fspi) { @@ -155,6 +171,134 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin, return 7; } +#define SPI_IMX2_3_CTRL 0x08 +#define SPI_IMX2_3_CTRL_ENABLE (1 << 0) +#define SPI_IMX2_3_CTRL_XCH (1 << 2) +#define SPI_IMX2_3_CTRL_MODE_MASK (0xf << 4) +#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8 +#define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12 +#define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18) +#define SPI_IMX2_3_CTRL_BL_OFFSET 20 + +#define SPI_IMX2_3_CONFIG 0x0c +#define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) +#define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) +#define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) +#define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) + +#define SPI_IMX2_3_INT 0x10 +#define SPI_IMX2_3_INT_TEEN (1 << 0) +#define SPI_IMX2_3_INT_RREN (1 << 3) + +#define SPI_IMX2_3_STAT 0x18 +#define SPI_IMX2_3_STAT_RR (1 << 3) + +/* MX51 eCSPI */ +static unsigned int spi_imx2_3_clkdiv(unsigned int fin, unsigned int fspi) +{ + /* + * there are two 4-bit dividers, the pre-divider divides by + * $pre, the post-divider by 2^$post + */ + unsigned int pre, post; + + if (unlikely(fspi > fin)) + return 0; + + post = fls(fin) - fls(fspi); + if (fin > fspi << post) + post++; + + /* now we have: (fin <= fspi << post) with post being minimal */ + + post = max(4U, post) - 4; + if (unlikely(post > 0xf)) { + pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", + __func__, fspi, fin); + return 0xff; + } + + pre = DIV_ROUND_UP(fin, fspi << post) - 1; + + pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", + __func__, fin, fspi, post, pre); + return (pre << SPI_IMX2_3_CTRL_PREDIV_OFFSET) | + (post << SPI_IMX2_3_CTRL_POSTDIV_OFFSET); +} + +static void __maybe_unused spi_imx2_3_intctrl(struct spi_imx_data *spi_imx, int enable) +{ + unsigned val = 0; + + if (enable & MXC_INT_TE) + val |= SPI_IMX2_3_INT_TEEN; + + if (enable & MXC_INT_RR) + val |= SPI_IMX2_3_INT_RREN; + + writel(val, spi_imx->base + SPI_IMX2_3_INT); +} + +static void __maybe_unused spi_imx2_3_trigger(struct spi_imx_data *spi_imx) +{ + u32 reg; + + reg = readl(spi_imx->base + SPI_IMX2_3_CTRL); + reg |= SPI_IMX2_3_CTRL_XCH; + writel(reg, spi_imx->base + SPI_IMX2_3_CTRL); +} + +static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx, + struct spi_imx_config *config) +{ + u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0; + + /* + * The hardware seems to have a race condition when changing modes. The + * current assumption is that the selection of the channel arrives + * earlier in the hardware than the mode bits when they are written at + * the same time. + * So set master mode for all channels as we do not support slave mode. + */ + ctrl |= SPI_IMX2_3_CTRL_MODE_MASK; + + /* set clock speed */ + ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz); + + /* set chip select to use */ + ctrl |= SPI_IMX2_3_CTRL_CS(config->cs); + + ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET; + + cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs); + + if (config->mode & SPI_CPHA) + cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs); + + if (config->mode & SPI_CPOL) + cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs); + + if (config->mode & SPI_CS_HIGH) + cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs); + + writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL); + writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG); + + return 0; +} + +static int __maybe_unused spi_imx2_3_rx_available(struct spi_imx_data *spi_imx) +{ + return readl(spi_imx->base + SPI_IMX2_3_STAT) & SPI_IMX2_3_STAT_RR; +} + +static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx) +{ + /* drain receive buffer */ + while (spi_imx2_3_rx_available(spi_imx)) + readl(spi_imx->base + MXC_CSPIRXDATA); +} + #define MX31_INTREG_TEEN (1 << 0) #define MX31_INTREG_RREN (1 << 3) @@ -178,7 +322,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin, * the i.MX35 has a slightly different register layout for bits * we do not use here. */ -static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) +static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; @@ -190,7 +334,7 @@ static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) writel(val, spi_imx->base + MXC_CSPIINT); } -static void mx31_trigger(struct spi_imx_data *spi_imx) +static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; @@ -199,20 +343,16 @@ static void mx31_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } -static int mx31_config(struct spi_imx_data *spi_imx, +static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) { unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; + int cs = spi_imx->chipselect[config->cs]; reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << MX31_CSPICTRL_DR_SHIFT; - if (cpu_is_mx31()) - reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; - else if (cpu_is_mx25() || cpu_is_mx35()) { - reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; - reg |= MX31_CSPICTRL_SSCTL; - } + reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; if (config->mode & SPI_CPHA) reg |= MX31_CSPICTRL_PHA; @@ -220,23 +360,52 @@ static int mx31_config(struct spi_imx_data *spi_imx, reg |= MX31_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) reg |= MX31_CSPICTRL_SSPOL; - if (config->cs < 0) { - if (cpu_is_mx31()) - reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT; - else if (cpu_is_mx25() || cpu_is_mx35()) - reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; - } + if (cs < 0) + reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT; + + writel(reg, spi_imx->base + MXC_CSPICTRL); + + return 0; +} + +static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx, + struct spi_imx_config *config) +{ + unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; + int cs = spi_imx->chipselect[config->cs]; + + reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << + MX31_CSPICTRL_DR_SHIFT; + + reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; + reg |= MX31_CSPICTRL_SSCTL; + + if (config->mode & SPI_CPHA) + reg |= MX31_CSPICTRL_PHA; + if (config->mode & SPI_CPOL) + reg |= MX31_CSPICTRL_POL; + if (config->mode & SPI_CS_HIGH) + reg |= MX31_CSPICTRL_SSPOL; + if (cs < 0) + reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT; writel(reg, spi_imx->base + MXC_CSPICTRL); return 0; } -static int mx31_rx_available(struct spi_imx_data *spi_imx) +static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; } +static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx) +{ + /* drain receive buffer */ + while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR) + readl(spi_imx->base + MXC_CSPIRXDATA); +} + #define MX27_INTREG_RR (1 << 4) #define MX27_INTREG_TEEN (1 << 9) #define MX27_INTREG_RREN (1 << 13) @@ -250,7 +419,7 @@ static int mx31_rx_available(struct spi_imx_data *spi_imx) #define MX27_CSPICTRL_DR_SHIFT 14 #define MX27_CSPICTRL_CS_SHIFT 19 -static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) +static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; @@ -262,7 +431,7 @@ static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) writel(val, spi_imx->base + MXC_CSPIINT); } -static void mx27_trigger(struct spi_imx_data *spi_imx) +static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; @@ -271,10 +440,11 @@ static void mx27_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } -static int mx27_config(struct spi_imx_data *spi_imx, +static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) { unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; + int cs = spi_imx->chipselect[config->cs]; reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << MX27_CSPICTRL_DR_SHIFT; @@ -286,19 +456,24 @@ static int mx27_config(struct spi_imx_data *spi_imx, reg |= MX27_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) reg |= MX27_CSPICTRL_SSPOL; - if (config->cs < 0) - reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; + if (cs < 0) + reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT; writel(reg, spi_imx->base + MXC_CSPICTRL); return 0; } -static int mx27_rx_available(struct spi_imx_data *spi_imx) +static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; } +static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx) +{ + writel(1, spi_imx->base + MXC_RESET); +} + #define MX1_INTREG_RR (1 << 3) #define MX1_INTREG_TEEN (1 << 8) #define MX1_INTREG_RREN (1 << 11) @@ -310,7 +485,7 @@ static int mx27_rx_available(struct spi_imx_data *spi_imx) #define MX1_CSPICTRL_MASTER (1 << 10) #define MX1_CSPICTRL_DR_SHIFT 13 -static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) +static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; @@ -322,7 +497,7 @@ static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) writel(val, spi_imx->base + MXC_CSPIINT); } -static void mx1_trigger(struct spi_imx_data *spi_imx) +static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; @@ -331,7 +506,7 @@ static void mx1_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } -static int mx1_config(struct spi_imx_data *spi_imx, +static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) { unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; @@ -350,11 +525,73 @@ static int mx1_config(struct spi_imx_data *spi_imx, return 0; } -static int mx1_rx_available(struct spi_imx_data *spi_imx) +static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; } +static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) +{ + writel(1, spi_imx->base + MXC_RESET); +} + +/* + * These version numbers are taken from the Freescale driver. Unfortunately it + * doesn't support i.MX1, so this entry doesn't match the scheme. :-( + */ +static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = { +#ifdef CONFIG_SPI_IMX_VER_IMX1 + [SPI_IMX_VER_IMX1] = { + .intctrl = mx1_intctrl, + .config = mx1_config, + .trigger = mx1_trigger, + .rx_available = mx1_rx_available, + .reset = mx1_reset, + .fifosize = 8, + }, +#endif +#ifdef CONFIG_SPI_IMX_VER_0_0 + [SPI_IMX_VER_0_0] = { + .intctrl = mx27_intctrl, + .config = mx27_config, + .trigger = mx27_trigger, + .rx_available = mx27_rx_available, + .reset = spi_imx0_0_reset, + .fifosize = 8, + }, +#endif +#ifdef CONFIG_SPI_IMX_VER_0_4 + [SPI_IMX_VER_0_4] = { + .intctrl = mx31_intctrl, + .config = spi_imx0_4_config, + .trigger = mx31_trigger, + .rx_available = mx31_rx_available, + .reset = spi_imx0_4_reset, + .fifosize = 8, + }, +#endif +#ifdef CONFIG_SPI_IMX_VER_0_7 + [SPI_IMX_VER_0_7] = { + .intctrl = mx31_intctrl, + .config = spi_imx0_7_config, + .trigger = mx31_trigger, + .rx_available = mx31_rx_available, + .reset = spi_imx0_4_reset, + .fifosize = 8, + }, +#endif +#ifdef CONFIG_SPI_IMX_VER_2_3 + [SPI_IMX_VER_2_3] = { + .intctrl = spi_imx2_3_intctrl, + .config = spi_imx2_3_config, + .trigger = spi_imx2_3_trigger, + .rx_available = spi_imx2_3_rx_available, + .reset = spi_imx2_3_reset, + .fifosize = 64, + }, +#endif +}; + static void spi_imx_chipselect(struct spi_device *spi, int is_active) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); @@ -370,21 +607,21 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active) static void spi_imx_push(struct spi_imx_data *spi_imx) { - while (spi_imx->txfifo < 8) { + while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) { if (!spi_imx->count) break; spi_imx->tx(spi_imx); spi_imx->txfifo++; } - spi_imx->trigger(spi_imx); + spi_imx->devtype_data.trigger(spi_imx); } static irqreturn_t spi_imx_isr(int irq, void *dev_id) { struct spi_imx_data *spi_imx = dev_id; - while (spi_imx->rx_available(spi_imx)) { + while (spi_imx->devtype_data.rx_available(spi_imx)) { spi_imx->rx(spi_imx); spi_imx->txfifo--; } @@ -398,11 +635,12 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id) /* No data left to push, but still waiting for rx data, * enable receive data available interrupt. */ - spi_imx->intctrl(spi_imx, MXC_INT_RR); + spi_imx->devtype_data.intctrl( + spi_imx, MXC_INT_RR); return IRQ_HANDLED; } - spi_imx->intctrl(spi_imx, 0); + spi_imx->devtype_data.intctrl(spi_imx, 0); complete(&spi_imx->xfer_done); return IRQ_HANDLED; @@ -417,7 +655,7 @@ static int spi_imx_setupxfer(struct spi_device *spi, config.bpw = t ? t->bits_per_word : spi->bits_per_word; config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; config.mode = spi->mode; - config.cs = spi_imx->chipselect[spi->chip_select]; + config.cs = spi->chip_select; if (!config.speed_hz) config.speed_hz = spi->max_speed_hz; @@ -439,7 +677,7 @@ static int spi_imx_setupxfer(struct spi_device *spi, } else BUG(); - spi_imx->config(spi_imx, &config); + spi_imx->devtype_data.config(spi_imx, &config); return 0; } @@ -458,7 +696,7 @@ static int spi_imx_transfer(struct spi_device *spi, spi_imx_push(spi_imx); - spi_imx->intctrl(spi_imx, MXC_INT_TE); + spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE); wait_for_completion(&spi_imx->xfer_done); @@ -485,6 +723,42 @@ static void spi_imx_cleanup(struct spi_device *spi) { } +static struct platform_device_id spi_imx_devtype[] = { + { + .name = "imx1-cspi", + .driver_data = SPI_IMX_VER_IMX1, + }, { + .name = "imx21-cspi", + .driver_data = SPI_IMX_VER_0_0, + }, { + .name = "imx25-cspi", + .driver_data = SPI_IMX_VER_0_7, + }, { + .name = "imx27-cspi", + .driver_data = SPI_IMX_VER_0_0, + }, { + .name = "imx31-cspi", + .driver_data = SPI_IMX_VER_0_4, + }, { + .name = "imx35-cspi", + .driver_data = SPI_IMX_VER_0_7, + }, { + .name = "imx51-cspi", + .driver_data = SPI_IMX_VER_0_7, + }, { + .name = "imx51-ecspi", + .driver_data = SPI_IMX_VER_2_3, + }, { + .name = "imx53-cspi", + .driver_data = SPI_IMX_VER_0_7, + }, { + .name = "imx53-ecspi", + .driver_data = SPI_IMX_VER_2_3, + }, { + /* sentinel */ + } +}; + static int __devinit spi_imx_probe(struct platform_device *pdev) { struct spi_imx_master *mxc_platform_info; @@ -536,6 +810,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) init_completion(&spi_imx->xfer_done); + spi_imx->devtype_data = + spi_imx_devtype_data[pdev->id_entry->driver_data]; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "can't get platform resource\n"); @@ -556,7 +833,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) } spi_imx->irq = platform_get_irq(pdev, 0); - if (spi_imx->irq <= 0) { + if (spi_imx->irq < 0) { ret = -EINVAL; goto out_iounmap; } @@ -567,24 +844,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) goto out_iounmap; } - if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) { - spi_imx->intctrl = mx31_intctrl; - spi_imx->config = mx31_config; - spi_imx->trigger = mx31_trigger; - spi_imx->rx_available = mx31_rx_available; - } else if (cpu_is_mx27() || cpu_is_mx21()) { - spi_imx->intctrl = mx27_intctrl; - spi_imx->config = mx27_config; - spi_imx->trigger = mx27_trigger; - spi_imx->rx_available = mx27_rx_available; - } else if (cpu_is_mx1()) { - spi_imx->intctrl = mx1_intctrl; - spi_imx->config = mx1_config; - spi_imx->trigger = mx1_trigger; - spi_imx->rx_available = mx1_rx_available; - } else - BUG(); - spi_imx->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(spi_imx->clk)) { dev_err(&pdev->dev, "unable to get clock\n"); @@ -595,15 +854,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) clk_enable(spi_imx->clk); spi_imx->spi_clk = clk_get_rate(spi_imx->clk); - if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) - writel(1, spi_imx->base + MXC_RESET); - - /* drain receive buffer */ - if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) - while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR) - readl(spi_imx->base + MXC_CSPIRXDATA); + spi_imx->devtype_data.reset(spi_imx); - spi_imx->intctrl(spi_imx, 0); + spi_imx->devtype_data.intctrl(spi_imx, 0); ret = spi_bitbang_start(&spi_imx->bitbang); if (ret) { @@ -668,6 +921,7 @@ static struct platform_driver spi_imx_driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, }, + .id_table = spi_imx_devtype, .probe = spi_imx_probe, .remove = __devexit_p(spi_imx_remove), }; diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c index d0b8bde..66cba5f 100644 --- a/drivers/usb/gadget/fsl_mxc_udc.c +++ b/drivers/usb/gadget/fsl_mxc_udc.c @@ -21,6 +21,7 @@ static struct clk *mxc_ahb_clk; static struct clk *mxc_usb_clk; +static struct clk *mxc_phy_clk; int fsl_udc_clk_init(struct platform_device *pdev) { @@ -66,8 +67,28 @@ int fsl_udc_clk_init(struct platform_device *pdev) goto eenusb; } + /* "dr" device has its own clock on i.MX51 */ + if (cpu_is_mx51()) { + mxc_phy_clk = clk_get(&pdev->dev, "usb_phy1"); + if (IS_ERR(mxc_phy_clk)) { + dev_err(&pdev->dev, "clk_get(\"usb_phy1\") failed\n"); + ret = PTR_ERR(mxc_phy_clk); + goto egphy; + } + + ret = clk_enable(mxc_phy_clk); + if (ret < 0) { + dev_err(&pdev->dev, "clk_get(\"usb_phy1\") failed\n"); + goto eephy; + } + } + return 0; +eephy: + clk_put(mxc_phy_clk); + mxc_phy_clk = NULL; +egphy: eenusb: eclkrate: clk_put(mxc_usb_clk); @@ -87,6 +108,9 @@ void fsl_udc_clk_finalize(struct platform_device *pdev) /* ULPI transceivers don't need usbpll */ if (pdata->phy_mode == FSL_USB2_PHY_ULPI) { + clk_disable(mxc_phy_clk); + clk_put(mxc_phy_clk); + mxc_phy_clk = NULL; clk_disable(mxc_usb_clk); clk_put(mxc_usb_clk); mxc_usb_clk = NULL; @@ -95,6 +119,10 @@ void fsl_udc_clk_finalize(struct platform_device *pdev) void fsl_udc_clk_release(void) { + if (mxc_phy_clk) { + clk_disable(mxc_phy_clk); + clk_put(mxc_phy_clk); + } if (mxc_usb_clk) { clk_disable(mxc_usb_clk); clk_put(mxc_usb_clk); diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c index 7d0e7fb..826342f 100644 --- a/drivers/usb/gadget/fsl_udc_core.c +++ b/drivers/usb/gadget/fsl_udc_core.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2010 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All rights reserved. * * Author: Li Yang * Jiang Bo @@ -2239,8 +2239,9 @@ static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index, * all intialization operations implemented here except enabling usb_intr reg * board setup should have been done in the platform code */ -static int __init fsl_udc_probe(struct platform_device *pdev) +static int __devinit fsl_udc_probe(struct platform_device *pdev) { + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; struct resource *res; int ret = -ENODEV; unsigned int i; @@ -2251,6 +2252,11 @@ static int __init fsl_udc_probe(struct platform_device *pdev) return -ENODEV; } + if (!pdata) { + dev_err(&pdev->dev, "No platform data given, bailing out.\n"); + return -EINVAL; + } + udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL); if (udc_controller == NULL) { ERR("malloc udc failed\n"); @@ -2289,6 +2295,17 @@ static int __init fsl_udc_probe(struct platform_device *pdev) if (ret < 0) goto err_iounmap_noclk; + /* call platform specific init function */ + if (pdata->platform_init) { + ret = pdata->platform_init(pdev); + if (ret) { + dev_err(&pdev->dev, "platform init failed\n"); + goto err_platform_init; + } + /* platforms need some time to settle changed IO settings */ + mdelay(10); + } + /* Read Device Controller Capability Parameters register */ dccparams = fsl_readl(&dr_regs->dccparams); if (!(dccparams & DCCPARAMS_DC)) { @@ -2382,6 +2399,7 @@ err_free_irq: free_irq(udc_controller->irq, udc_controller); err_iounmap: fsl_udc_clk_release(); +err_platform_init: err_iounmap_noclk: iounmap(dr_regs); err_release_mem_region: diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index bd40277..9651b04 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -31,7 +31,7 @@ #define USBMODE_CM_HOST 3 struct ehci_mxc_priv { - struct clk *usbclk, *ahbclk; + struct clk *usbclk, *ahbclk, *phy1clk; struct usb_hcd *hcd; }; @@ -51,6 +51,8 @@ static int ehci_mxc_setup(struct usb_hcd *hcd) /* cache this readonly data; minimize chip reads */ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + hcd->has_tt = 1; + retval = ehci_halt(ehci); if (retval) return retval; @@ -60,8 +62,6 @@ static int ehci_mxc_setup(struct usb_hcd *hcd) if (retval) return retval; - hcd->has_tt = 1; - ehci->sbrn = 0x20; ehci_reset(ehci); @@ -95,6 +95,7 @@ static const struct hc_driver ehci_mxc_hc_driver = { .urb_enqueue = ehci_urb_enqueue, .urb_dequeue = ehci_urb_dequeue, .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, /* * scheduling support @@ -110,6 +111,7 @@ static const struct hc_driver ehci_mxc_hc_driver = { .bus_resume = ehci_bus_resume, .relinquish_port = ehci_relinquish_port, .port_handed_over = ehci_port_handed_over, + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, }; static int ehci_mxc_drv_probe(struct platform_device *pdev) @@ -163,17 +165,6 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) goto err_ioremap; } - /* call platform specific init function */ - if (pdata->init) { - ret = pdata->init(pdev); - if (ret) { - dev_err(dev, "platform init failed\n"); - goto err_init; - } - /* platforms need some time to settle changed IO settings */ - mdelay(10); - } - /* enable clocks */ priv->usbclk = clk_get(dev, "usb"); if (IS_ERR(priv->usbclk)) { @@ -182,7 +173,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) } clk_enable(priv->usbclk); - if (!cpu_is_mx35()) { + if (!cpu_is_mx35() && !cpu_is_mx25()) { priv->ahbclk = clk_get(dev, "usb_ahb"); if (IS_ERR(priv->ahbclk)) { ret = PTR_ERR(priv->ahbclk); @@ -191,6 +182,30 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) clk_enable(priv->ahbclk); } + /* "dr" device has its own clock on i.MX51 */ + if (cpu_is_mx51() && (pdev->id == 0)) { + priv->phy1clk = clk_get(dev, "usb_phy1"); + if (IS_ERR(priv->phy1clk)) { + ret = PTR_ERR(priv->phy1clk); + goto err_clk_phy; + } + clk_enable(priv->phy1clk); + } + + + /* call platform specific init function */ + if (pdata->init) { + ret = pdata->init(pdev); + if (ret) { + dev_err(dev, "platform init failed\n"); + goto err_init; + } + /* platforms need some time to settle changed IO settings */ + mdelay(10); + } + + + /* set USBMODE to host mode */ temp = readl(hcd->regs + USBMODE_OFFSET); writel(temp | USBMODE_CM_HOST, hcd->regs + USBMODE_OFFSET); @@ -233,6 +248,11 @@ err_add: if (pdata && pdata->exit) pdata->exit(pdev); err_init: + if (priv->phy1clk) { + clk_disable(priv->phy1clk); + clk_put(priv->phy1clk); + } +err_clk_phy: if (priv->ahbclk) { clk_disable(priv->ahbclk); clk_put(priv->ahbclk); @@ -276,6 +296,10 @@ static int __exit ehci_mxc_drv_remove(struct platform_device *pdev) clk_disable(priv->ahbclk); clk_put(priv->ahbclk); } + if (priv->phy1clk) { + clk_disable(priv->phy1clk); + clk_put(priv->phy1clk); + } kfree(priv); diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c index dd9ec0b..b0974ba 100644 --- a/drivers/usb/storage/usb.c +++ b/drivers/usb/storage/usb.c @@ -335,7 +335,7 @@ static int usb_stor_control_thread(void * __us) /* we've got a command, let's do it! */ else { US_DEBUGP(usb_stor_show_command(us->srb)); -#ifdef CONFIG_MACH_MX51_BABBAGE +#if defined(CONFIG_MACH_MX51_BABBAGE) || defined(CONFIG_MACH_VMX51) if (us->srb->cmnd[0] != 0x85) #endif us->proto_handler(us->srb, us); diff --git a/drivers/video/mxc/Kconfig b/drivers/video/mxc/Kconfig index e2b79fa..e7cefec 100644 --- a/drivers/video/mxc/Kconfig +++ b/drivers/video/mxc/Kconfig @@ -42,6 +42,14 @@ config FB_MXC_SEIKO_WVGA_SYNC_PANEL depends on FB_MXC_SYNC_PANEL tristate "SEIKO WVGA Panel" +config FB_MXC_DATAIMAGE_WVGA_SYNC_PANEL + depends on FB_MXC_SYNC_PANEL + tristate "DATAIMAGE WVGA Panel" + +config FB_MXC_OPTREX_VGA_SYNC_PANEL + depends on FB_MXC_SYNC_PANEL + tristate "OPTREX VGA Panel" + config FB_MXC_SII902X depends on FB_MXC_SYNC_PANEL tristate "Si Image SII9022 DVI/HDMI Interface Chip" @@ -54,6 +62,17 @@ config FB_MXC_TVOUT_CH7024 tristate "CH7024 TV Out Encoder" depends on FB_MXC_SYNC_PANEL +config FB_MXC_FIX_SYNC_PANEL + depends on FB_MXC_SYNC_PANEL + tristate "FIX Clock sync on falling edge" + help + This option with redefine FB_SYNC_CLK_LAT_FALL as FB_SYNC_BROADCAST + making FB_SYNC_BROADCAST option not usable anymore. This is quick bug + fix for some userspace applications. + + If you plan to use the TFT LCD display with Ubuntu 10.04, say + Y here. + config FB_MXC_LOW_PWR_DISPLAY bool "Low Power Display Refresh Mode" depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM diff --git a/drivers/video/mxc/Makefile b/drivers/video/mxc/Makefile index 723001a..38026a7 100644 --- a/drivers/video/mxc/Makefile +++ b/drivers/video/mxc/Makefile @@ -20,6 +20,8 @@ endif obj-$(CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL) += mxcfb_epson_vga.o obj-$(CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL) += mxcfb_claa_wvga.o obj-$(CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL) += mxcfb_seiko_wvga.o +obj-$(CONFIG_FB_MXC_DATAIMAGE_WVGA_SYNC_PANEL) += mxcfb_dataimage_wvga.o +obj-$(CONFIG_FB_MXC_OPTREX_VGA_SYNC_PANEL) += mxcfb_optrex_vga.o obj-$(CONFIG_FB_MXC_TVOUT_CH7024) += ch7024.o obj-$(CONFIG_FB_MXC_CH7026) += mxcfb_ch7026.o obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c index 5211796..f2d0c78 100644 --- a/drivers/video/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/mxc/mxc_ipuv3_fb.c @@ -2051,9 +2051,16 @@ static int mxcfb_option_setup(struct fb_info *info, char *options) mxcfbi->ipu_int_clk = true; continue; } - if (!strncmp(opt, "bpp=", 4)) - mxcfbi->default_bpp = - simple_strtoul(opt + 4, NULL, 0); + if (!strncmp(opt, "bpp=", 4)) { + mxcfbi->default_bpp = simple_strtoul(opt + 4, NULL, 0); + continue; + } + if (!strncmp(opt, "noaccel", 7)) { + continue; + } + if (!strncmp(opt, "accel", 5)) { + continue; + } else mxcfbi->fb_mode_str = opt; } diff --git a/drivers/video/mxc/mxcfb_dataimage_wvga.c b/drivers/video/mxc/mxcfb_dataimage_wvga.c index e69de29..cfeec09 100644 --- a/drivers/video/mxc/mxcfb_dataimage_wvga.c +++ b/drivers/video/mxc/mxcfb_dataimage_wvga.c @@ -0,0 +1,251 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxcfb_dataimage_wvga.c + * + * @brief MXC Frame buffer driver for SDC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void lcd_poweron(void); +static void lcd_poweroff(void); + +static struct platform_device *plcd_dev; +static struct regulator *io_reg = NULL; +static struct regulator *core_reg = NULL; +static int lcd_on; + +static struct fb_videomode video_modes[] = { + { + // FG0700K5DSSWAGT1 + .name = "DATAIMAGE-WVGA", + .refresh = 59, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 160, // Back porch + .right_margin = 54, // Front porch + .upper_margin = 10, // Back porch + .lower_margin = 10, // Front porch + .hsync_len = 86, + .vsync_len = 4, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +}; + +static void lcd_init_fb(struct fb_info *info) +{ + struct fb_var_screeninfo var; + + memset(&var, 0, sizeof(var)); + + fb_videomode_to_var(&var, &video_modes[0]); + + var.activate = FB_ACTIVATE_ALL; + var.yres_virtual = var.yres * 3; + + acquire_console_sem(); + info->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(info, &var); + info->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); +} + +static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + + if (strcmp(event->info->fix.id, "DISP3 BG") && + strcmp(event->info->fix.id, "mxc_elcdif_fb")) + return 0; + + switch (val) { + case FB_EVENT_FB_REGISTERED: + lcd_init_fb(event->info); + fb_show_logo(event->info, 0); + lcd_poweron(); + break; + case FB_EVENT_BLANK: + if ((event->info->var.xres != 800) || + (event->info->var.yres != 480)) { + break; + } + if (*((int *)event->data) == FB_BLANK_UNBLANK) { + lcd_poweron(); + } else { + lcd_poweroff(); + } + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = lcd_fb_event, +}; + +/*! + * This function is called whenever the LCD device is detected. + * + * @param pdev the platform data device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit lcd_probe(struct platform_device *pdev) +{ + int i; + struct mxc_lcd_platform_data *plat = pdev->dev.platform_data; + + if (plat) { + if (plat->reset) + plat->reset(); + + io_reg = regulator_get(&pdev->dev, plat->io_reg); + if (IS_ERR(io_reg)) + io_reg = NULL; + core_reg = regulator_get(&pdev->dev, plat->core_reg); + if (!IS_ERR(core_reg)) { + regulator_set_voltage(io_reg, 1800000, 1800000); + } else { + core_reg = NULL; + } + } + + for (i = 0; i < num_registered_fb; i++) { + if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0 || + strcmp(registered_fb[i]->fix.id, "mxc_elcdif_fb") == 0) { + lcd_init_fb(registered_fb[i]); + fb_show_logo(registered_fb[i], 0); + lcd_poweron(); + } else if (strcmp(registered_fb[i]->fix.id, "DISP3 FG") == 0) { + lcd_init_fb(registered_fb[i]); + } + } + + fb_register_client(&nb); + + plcd_dev = pdev; + + return 0; +} + +static int __devexit lcd_remove(struct platform_device *pdev) +{ + fb_unregister_client(&nb); + lcd_poweroff(); + if (io_reg) + regulator_put(io_reg); + if (core_reg) + regulator_put(core_reg); + + return 0; +} + +#ifdef CONFIG_PM +static int lcd_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int lcd_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define lcd_suspend NULL +#define lcd_resume NULL +#endif + +/*! + * platform driver structure for DATAIMAGE WVGA + */ +static struct platform_driver lcd_driver = { + .driver = { + .name = "lcd_dataimage"}, + .probe = lcd_probe, + .remove = __devexit_p(lcd_remove), + .suspend = lcd_suspend, + .resume = lcd_resume, +}; + +/* + * Send Power On commands + * + */ +static void lcd_poweron(void) +{ + if (lcd_on) + return; + + dev_dbg(&plcd_dev->dev, "turning on LCD\n"); + if (core_reg) + regulator_enable(core_reg); + if (io_reg) + regulator_enable(io_reg); + lcd_on = 1; +} + +/* + * Send Power Off commands to L4F00242T03 + * + */ +static void lcd_poweroff(void) +{ + lcd_on = 0; + dev_dbg(&plcd_dev->dev, "turning off LCD\n"); + if (io_reg) + regulator_disable(io_reg); + if (core_reg) + regulator_disable(core_reg); +} + +static int __init dataimage_lcd_init(void) +{ + return platform_driver_register(&lcd_driver); +} + +static void __exit dataimage_lcd_exit(void) +{ + platform_driver_unregister(&lcd_driver); +} + +module_init(dataimage_lcd_init); +module_exit(dataimage_lcd_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DATAIMAGE WVGA LCD init driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/mxcfb_optrex_vga.c b/drivers/video/mxc/mxcfb_optrex_vga.c index e69de29..6912a5e 100644 --- a/drivers/video/mxc/mxcfb_optrex_vga.c +++ b/drivers/video/mxc/mxcfb_optrex_vga.c @@ -0,0 +1,251 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxcfb_optrex_vga.c + * + * @brief MXC Frame buffer driver for SDC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void lcd_poweron(void); +static void lcd_poweroff(void); + +static struct platform_device *plcd_dev; +static struct regulator *io_reg = NULL; +static struct regulator *core_reg = NULL; +static int lcd_on; + +static struct fb_videomode video_modes[] = { + { + // t-51750gd065j-lw + .name = "OPTREX-VGA", + .refresh = 59, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(24000), + .left_margin = 84, // Back porch + .right_margin = 10, // Front porch + .upper_margin = 20, // Back porch + .lower_margin = 20, // Front porch + .hsync_len = 34, + .vsync_len = 5, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +}; + +static void lcd_init_fb(struct fb_info *info) +{ + struct fb_var_screeninfo var; + + memset(&var, 0, sizeof(var)); + + fb_videomode_to_var(&var, &video_modes[0]); + + var.activate = FB_ACTIVATE_ALL; + var.yres_virtual = var.yres * 3; + + acquire_console_sem(); + info->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(info, &var); + info->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); +} + +static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + + if (strcmp(event->info->fix.id, "DISP3 BG") && + strcmp(event->info->fix.id, "mxc_elcdif_fb")) + return 0; + + switch (val) { + case FB_EVENT_FB_REGISTERED: + lcd_init_fb(event->info); + fb_show_logo(event->info, 0); + lcd_poweron(); + break; + case FB_EVENT_BLANK: + if ((event->info->var.xres != 640) || + (event->info->var.yres != 480)) { + break; + } + if (*((int *)event->data) == FB_BLANK_UNBLANK) { + lcd_poweron(); + } else { + lcd_poweroff(); + } + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = lcd_fb_event, +}; + +/*! + * This function is called whenever the LCD device is detected. + * + * @param pdev the platform data device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit lcd_probe(struct platform_device *pdev) +{ + int i; + struct mxc_lcd_platform_data *plat = pdev->dev.platform_data; + + if (plat) { + if (plat->reset) + plat->reset(); + + io_reg = regulator_get(&pdev->dev, plat->io_reg); + if (IS_ERR(io_reg)) + io_reg = NULL; + core_reg = regulator_get(&pdev->dev, plat->core_reg); + if (!IS_ERR(core_reg)) { + regulator_set_voltage(io_reg, 1800000, 1800000); + } else { + core_reg = NULL; + } + } + + for (i = 0; i < num_registered_fb; i++) { + if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0 || + strcmp(registered_fb[i]->fix.id, "mxc_elcdif_fb") == 0) { + lcd_init_fb(registered_fb[i]); + fb_show_logo(registered_fb[i], 0); + lcd_poweron(); + } else if (strcmp(registered_fb[i]->fix.id, "DISP3 FG") == 0) { + lcd_init_fb(registered_fb[i]); + } + } + + fb_register_client(&nb); + + plcd_dev = pdev; + + return 0; +} + +static int __devexit lcd_remove(struct platform_device *pdev) +{ + fb_unregister_client(&nb); + lcd_poweroff(); + if (io_reg) + regulator_put(io_reg); + if (core_reg) + regulator_put(core_reg); + + return 0; +} + +#ifdef CONFIG_PM +static int lcd_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int lcd_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define lcd_suspend NULL +#define lcd_resume NULL +#endif + +/*! + * platform driver structure for OPTREX VGA + */ +static struct platform_driver lcd_driver = { + .driver = { + .name = "lcd_optrex"}, + .probe = lcd_probe, + .remove = __devexit_p(lcd_remove), + .suspend = lcd_suspend, + .resume = lcd_resume, +}; + +/* + * Send Power On commands + * + */ +static void lcd_poweron(void) +{ + if (lcd_on) + return; + + dev_dbg(&plcd_dev->dev, "turning on LCD\n"); + if (core_reg) + regulator_enable(core_reg); + if (io_reg) + regulator_enable(io_reg); + lcd_on = 1; +} + +/* + * Send Power Off commands to L4F00242T03 + * + */ +static void lcd_poweroff(void) +{ + lcd_on = 0; + dev_dbg(&plcd_dev->dev, "turning off LCD\n"); + if (io_reg) + regulator_disable(io_reg); + if (core_reg) + regulator_disable(core_reg); +} + +static int __init dataimage_lcd_init(void) +{ + return platform_driver_register(&lcd_driver); +} + +static void __exit dataimage_lcd_exit(void) +{ + platform_driver_unregister(&lcd_driver); +} + +module_init(dataimage_lcd_init); +module_exit(dataimage_lcd_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OPTREX VGA LCD init driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mxcfb.h b/include/linux/mxcfb.h index 3c70c00..69a5e7f 100644 --- a/include/linux/mxcfb.h +++ b/include/linux/mxcfb.h @@ -24,7 +24,11 @@ #include #define FB_SYNC_OE_LOW_ACT 0x80000000 +#if defined(FB_MXC_FIX_SYNC_PANEL) #define FB_SYNC_CLK_LAT_FALL 0x40000000 +#else +#define FB_SYNC_CLK_LAT_FALL FB_SYNC_BROADCAST +#endif #define FB_SYNC_DATA_INVERT 0x20000000 #define FB_SYNC_CLK_IDLE_EN 0x10000000 #define FB_SYNC_SHARP_MODE 0x08000000 diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index bb94c65..871d59e 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -26,9 +26,14 @@ #include #include #include +#include #include "sgtl5000.h" +#include +/* I2C code related */ +static unsigned i2c_timeout = 250; + struct sgtl5000_priv { int sysclk; int master; @@ -106,12 +111,21 @@ static unsigned int sgtl5000_hw_read(struct snd_soc_codec *codec, {addr, flags, 2, buf0}, {addr, flags | I2C_M_RD, 2, buf1}, }; + unsigned long timeout, read_time; sgtl5000->need_clk_for_access = 1; sgtl5000_clock_gating(codec, 1); buf0[0] = (reg & 0xff00) >> 8; buf0[1] = reg & 0xff; - i2c_ret = i2c_transfer(client->adapter, msg, 2); + + timeout = jiffies + msecs_to_jiffies(i2c_timeout); + do { + read_time = jiffies; + i2c_ret = i2c_transfer(client->adapter, msg, 2); + // REVISIT: at HZ=100, this is sloooow + msleep(1); + } while (time_before(read_time, timeout) && i2c_ret != 2); + sgtl5000->need_clk_for_access = 0; sgtl5000_clock_gating(codec, 0); if (i2c_ret < 0) { @@ -1267,6 +1281,12 @@ static __devinit int sgtl5000_i2c_probe(struct i2c_client *client, sgtl5000->vddd = 0; /* use internal regulator */ } + if(machine_is_vmx51()) { + sgtl5000->vdda = 3300; + sgtl5000->vddio = 3300; + sgtl5000->vddd = 0; /* use internal regulator */ + } + msleep(1); val = sgtl5000_read(codec, SGTL5000_CHIP_ID);