diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/config.h barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/config.h --- barebox-2011.06.0/arch/arm/boards/vmx51/config.h 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/config.h 2011-06-10 13:13:22.582039195 +0200 @@ -0,0 +1,24 @@ +/** + * @file + * @brief Global defintions for the ARM i.MX51 based babbage board + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/env/bin/boot barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/env/bin/boot --- barebox-2011.06.0/arch/arm/boards/vmx51/env/bin/boot 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/env/bin/boot 2011-06-10 13:13:22.594509286 +0200 @@ -0,0 +1,65 @@ +#!/bin/sh + +. /env/config + +image=/dev/nand0.kernel.bb + +if [ x$1 = xjffS2 ]; then + root=jffs2 + kernel=nand +fi + +if [ x$1 = xubifs ]; then + root=ubifs + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net + image=$zimage +fi + +if [ $# = 2 ]; then + image=$2 +fi + +if [ x$ip = xdhcp ]; then + if [ x$root = xnet ]; then + bootargs="$bootargs ip=dhcp" + fi +else + if [ x$ip = xoff ]; then + bootargs="$bootargs ip=off" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +fi + +if [ x$root = xjffs2 ]; then + bootargs="$bootargs root=/dev/mtdblock$rootpartnum_nand rootfstype=jffs2" +fi + +if [ x$root = xubifs ]; then + bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum_nand rootfstype=ubifs" +fi + +if [ x$root = xnet ]; then + bootargs="$bootargs root=/dev/nfs" + if [ ! -z "$rootpath" ]; then + bootargs="$bootargs nfsroot=$eth0.serverip:$rootpath" + fi +fi + +bootargs="$bootargs mtdparts=mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $image zImage || exit 1 + bootz zImage +else + bootz $image +fi + diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/env/bin/init barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/env/bin/init --- barebox-2011.06.0/arch/arm/boards/vmx51/env/bin/init 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/env/bin/init 2011-06-10 13:13:22.594509286 +0200 @@ -0,0 +1,40 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # hush workaround + nand0_parts="/dev/nand0.*" + nand -a $nand0_parts +fi + +if [ -f /env/logo.bmp ]; then + bmp /env/logo.bmp +elif [ -f /env/logo.bmp.lzo ]; then + unlzo /env/logo.bmp.lzo /logo.bmp + bmp /logo.bmp +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "No MAC address set for eth0. Please enter the one found on your module: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" + saveenv +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + exit +fi + +boot + + + diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/env/bin/update barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/env/bin/update --- barebox-2011.06.0/arch/arm/boards/vmx51/env/bin/update 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/env/bin/update 2011-06-10 13:13:22.594509286 +0200 @@ -0,0 +1,54 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xbarebox ]; then + image=$barebox + part=/dev/nand0.barebox.bb +fi + +if [ x$1 = xkernel ]; then + image=$zimage + part=/dev/nand0.kernel.bb +fi + +if [ x$1 = xrootfs ]; then + image=$rootfs + part=/dev/nand0.rootfs.bb +fi + +if [ -z "$part" -o -z "$image" ]; then + echo "update barebox|kernel|rootfs []" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 2 ]; then + image=$2 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part + diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/env/config barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/env/config --- barebox-2011.06.0/arch/arm/boards/vmx51/env/config 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/env/config 2011-06-10 13:13:22.594509286 +0200 @@ -0,0 +1,28 @@ +#!/bin/sh + +# can be either 'net' or 'jffs2' or 'ubifs' +kernel=nand +root=ubifs + +basedir=vmx51 +barebox=$basedir/barebox.bin +zimage=$basedir/zImage +rootfs=$basedir/rootfs.bin + +autoboot_timeout=3 + +bootargs="console=ttymxc0,115200 otg_mode=host" + +nand_parts="256k(barebox)ro,768k(bareboxenv),3M(kernel),-(rootfs)" +rootpartnum_nand=4 +ubiroot="rootfs" + +# ip=off|static|dhcp +# use 'dhcp' to do dhcp in barebox and in kernel +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/flash_header.c barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/flash_header.c --- barebox-2011.06.0/arch/arm/boards/vmx51/flash_header.c 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/flash_header.c 2011-07-07 01:28:32.396573454 +0200 @@ -0,0 +1,96 @@ +#include +#include + +extern unsigned long _stext; + +void __naked __flash_header_start go(void) +{ + __asm__ __volatile__("b exception_vectors\n"); +} + +struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { + { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, }, + { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, }, + { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, }, + { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, + { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, + { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, }, + { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, }, + { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, }, +/* Set drive strength to MAX */ + { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, +/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ +/* CAS=3, BL=4 */ + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, +/* { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad090, }, */ + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ac0d0, }, + { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, }, + { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, }, +/* Init DRAM on CS0 */ + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, +/* Init DRAM on CS1 */ + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, +/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ +/* CAS=3, BL=4 */ + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, +/* { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad690, }, */ + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ac6d0, }, + { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, +}; + +#define APP_DEST 0x90000000 + +struct imx_flash_header __flash_header_section flash_header = { + .app_code_jump_vector = APP_DEST + 0x2000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = APP_DEST, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof (dcd_entry), +}; + +unsigned long __image_len_section barebox_len = 0x40000; + diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/fslmx51.h barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/fslmx51.h --- barebox-2011.06.0/arch/arm/boards/vmx51/fslmx51.h 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/fslmx51.h 2011-06-10 13:13:22.604508183 +0200 @@ -0,0 +1,503 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_MX51_H__ +#define __ASM_ARCH_MXC_MX51_H__ + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ +/* + * Graphics Memory of GPU + */ +#define GPU_BASE_ADDR 0x20000000 +#define GPU_CTRL_BASE_ADDR 0x30000000 +#define IPU_CTRL_BASE_ADDR 0x40000000 +/* + * Debug + */ +#define DEBUG_BASE_ADDR 0x60000000 +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x70000000 + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x73F00000 + +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x83F00000 + +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) +#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) + +#define TZIC_BASE_ADDR 0x8FFFC000 + +/* + * Memory regions and CS + */ +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define CS0_BASE_ADDR 0xB0000000 +#define CS1_BASE_ADDR 0xB8000000 +#define CS2_BASE_ADDR 0xC0000000 +#define CS3_BASE_ADDR 0xC8000000 +#define CS4_BASE_ADDR 0xCC000000 +#define CS5_BASE_ADDR 0xCE000000 + +/* + * NFC + */ +#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ + +/*! + * defines for SPBA modules + */ +#define SPBA_SDHC1 0x04 +#define SPBA_SDHC2 0x08 +#define SPBA_UART3 0x0C +#define SPBA_CSPI1 0x10 +#define SPBA_SSI2 0x14 +#define SPBA_SDHC3 0x20 +#define SPBA_SDHC4 0x24 +#define SPBA_SPDIF 0x28 +#define SPBA_ATA 0x30 +#define SPBA_SLIM 0x34 +#define SPBA_HSI2C 0x38 +#define SPBA_CTRL 0x3C + +/* + * Interrupt numbers + */ +#define MXC_INT_BASE 0 +#define MXC_INT_RESV0 0 +#define MXC_INT_MMC_SDHC1 1 +#define MXC_INT_MMC_SDHC2 2 +#define MXC_INT_MMC_SDHC3 3 +#define MXC_INT_MMC_SDHC4 4 +#define MXC_INT_RESV5 5 +#define MXC_INT_SDMA 6 +#define MXC_INT_IOMUX 7 +#define MXC_INT_NFC 8 +#define MXC_INT_VPU 9 +#define MXC_INT_IPU_ERR 10 +#define MXC_INT_IPU_SYN 11 +#define MXC_INT_GPU 12 +#define MXC_INT_RESV13 13 +#define MXC_INT_USB_H1 14 +#define MXC_INT_EMI 15 +#define MXC_INT_USB_H2 16 +#define MXC_INT_USB_H3 17 +#define MXC_INT_USB_OTG 18 +#define MXC_INT_SAHARA_H0 19 +#define MXC_INT_SAHARA_H1 20 +#define MXC_INT_SCC_SMN 21 +#define MXC_INT_SCC_STZ 22 +#define MXC_INT_SCC_SCM 23 +#define MXC_INT_SRTC_NTZ 24 +#define MXC_INT_SRTC_TZ 25 +#define MXC_INT_RTIC 26 +#define MXC_INT_CSU 27 +#define MXC_INT_SLIM_B 28 +#define MXC_INT_SSI1 29 +#define MXC_INT_SSI2 30 +#define MXC_INT_UART1 31 +#define MXC_INT_UART2 32 +#define MXC_INT_UART3 33 +#define MXC_INT_RESV34 34 +#define MXC_INT_RESV35 35 +#define MXC_INT_CSPI1 36 +#define MXC_INT_CSPI2 37 +#define MXC_INT_CSPI 38 +#define MXC_INT_GPT 39 +#define MXC_INT_EPIT1 40 +#define MXC_INT_EPIT2 41 +#define MXC_INT_GPIO1_INT7 42 +#define MXC_INT_GPIO1_INT6 43 +#define MXC_INT_GPIO1_INT5 44 +#define MXC_INT_GPIO1_INT4 45 +#define MXC_INT_GPIO1_INT3 46 +#define MXC_INT_GPIO1_INT2 47 +#define MXC_INT_GPIO1_INT1 48 +#define MXC_INT_GPIO1_INT0 49 +#define MXC_INT_GPIO1_LOW 50 +#define MXC_INT_GPIO1_HIGH 51 +#define MXC_INT_GPIO2_LOW 52 +#define MXC_INT_GPIO2_HIGH 53 +#define MXC_INT_GPIO3_LOW 54 +#define MXC_INT_GPIO3_HIGH 55 +#define MXC_INT_GPIO4_LOW 56 +#define MXC_INT_GPIO4_HIGH 57 +#define MXC_INT_WDOG1 58 +#define MXC_INT_WDOG2 59 +#define MXC_INT_KPP 60 +#define MXC_INT_PWM1 61 +#define MXC_INT_I2C1 62 +#define MXC_INT_I2C2 63 +#define MXC_INT_HS_I2C 64 +#define MXC_INT_RESV65 65 +#define MXC_INT_RESV66 66 +#define MXC_INT_SIM_IPB 67 +#define MXC_INT_SIM_DAT 68 +#define MXC_INT_IIM 69 +#define MXC_INT_ATA 70 +#define MXC_INT_CCM1 71 +#define MXC_INT_CCM2 72 +#define MXC_INT_GPC1 73 +#define MXC_INT_GPC2 74 +#define MXC_INT_SRC 75 +#define MXC_INT_NM 76 +#define MXC_INT_PMU 77 +#define MXC_INT_CTI_IRQ 78 +#define MXC_INT_CTI1_TG0 79 +#define MXC_INT_CTI1_TG1 80 +#define MXC_INT_MCG_ERR 81 +#define MXC_INT_MCG_TMR 82 +#define MXC_INT_MCG_FUNC 83 +#define MXC_INT_RESV84 84 +#define MXC_INT_RESV85 85 +#define MXC_INT_RESV86 86 +#define MXC_INT_FEC 87 +#define MXC_INT_OWIRE 88 +#define MXC_INT_CTI1_TG2 89 +#define MXC_INT_SJC 90 +#define MXC_INT_SPDIF 91 +#define MXC_INT_TVE 92 +#define MXC_INT_FIRI 93 +#define MXC_INT_PWM2 94 +#define MXC_INT_SLIM_EXP 95 +#define MXC_INT_SSI3 96 +#define MXC_INT_RESV97 97 +#define MXC_INT_CTI1_TG3 98 +#define MXC_INT_SMC_RX 99 +#define MXC_INT_VPU_IDLE 100 +#define MXC_INT_RESV101 101 +#define MXC_INT_GPU_IDLE 102 + +#define MXC_MAX_INT_LINES 128 + +#define MXC_GPIO_INT_BASE (MXC_MAX_INT_LINES) + +/*! + * Number of GPIO port as defined in the IC Spec + */ +#define GPIO_PORT_NUM 4 +/*! + * Number of GPIO pins per port + */ +#define GPIO_NUM_PIN 32 + +#define MXC_GPIO_SPLIT_IRQ_2 + +#define IIM_SREV 0x24 +#define ROM_SI_REV 0x48 + +#define NFC_BUF_SIZE 0x1000 + +/* WEIM registers */ +#define CSGCR1 0x00 +#define CSGCR2 0x04 +#define CSRCR1 0x08 +#define CSRCR2 0x0C +#define CSWCR1 0x10 + +/* M4IF */ +#define M4IF_FBPM0 0x40 +#define M4IF_FIDBP 0x48 + +/* ESDCTL */ +#define ESDCTL_ESDCTL0 0x00 +#define ESDCTL_ESDCFG0 0x04 +#define ESDCTL_ESDCTL1 0x08 +#define ESDCTL_ESDCFG1 0x0C +#define ESDCTL_ESDMISC 0x10 +#define ESDCTL_ESDSCR 0x14 +#define ESDCTL_ESDCDLY1 0x20 +#define ESDCTL_ESDCDLY2 0x24 +#define ESDCTL_ESDCDLY3 0x28 +#define ESDCTL_ESDCDLY4 0x2C +#define ESDCTL_ESDCDLY5 0x30 +#define ESDCTL_ESDCDLYGD 0x34 + +/* CCM */ +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CMEOR 0x84 + +/* DPLL */ +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_MFNMINUS 0x14 +#define PLL_DP_MFNPLUS 0x18 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 +#define PLL_DP_TOGC 0x28 +#define PLL_DP_DESTAT 0x2C + +/* Assuming 24MHz input clock with doubler ON */ +/* MFI PDF */ +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_850 (48 - 1) +#define DP_MFN_850 41 + +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_800 (3 - 1) +#define DP_MFN_800 1 + +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) +#define DP_MFD_700 (24 - 1) +#define DP_MFN_700 7 + +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_665 (96 - 1) +#define DP_MFN_665 89 + +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) +#define DP_MFD_532 (24 - 1) +#define DP_MFN_532 13 + +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) +#define DP_MFD_400 (3 - 1) +#define DP_MFN_400 1 + +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) +#define DP_MFD_216 (4 - 1) +#define DP_MFN_216 3 + +/* IIM */ +#define IIM_STAT_OFF 0x00 +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) +#define IIM_STATM_OFF 0x04 +#define IIM_ERR_OFF 0x08 +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) +#define IIM_EMASK_OFF 0x0C +#define IIM_FCTL_OFF 0x10 +#define IIM_UA_OFF 0x14 +#define IIM_LA_OFF 0x18 +#define IIM_SDAT_OFF 0x1C +#define IIM_PREV_OFF 0x20 +#define IIM_SREV_OFF 0x24 +#define IIM_PREG_P_OFF 0x28 +#define IIM_SCS0_OFF 0x2C +#define IIM_SCS1_P_OFF 0x30 +#define IIM_SCS2_OFF 0x34 +#define IIM_SCS3_P_OFF 0x38 + +#define IIM_PROD_REV_SH 3 +#define IIM_PROD_REV_LEN 5 +#define IIM_SREV_REV_SH 4 +#define IIM_SREV_REV_LEN 4 +#define PROD_SIGNATURE_MX51 0x1 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_5 0x25 +#define CHIP_REV_3_0 0x30 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#define BOARD_VER_OFFSET 0x8 + +#define NAND_FLASH_BOOT 0x10000000 +#define SPI_NOR_FLASH_BOOT 0x80000000 +#define MMC_FLASH_BOOT 0x40000000 + +#ifndef __ASSEMBLER__ + +enum boot_device { + UNKNOWN_BOOT = -1, + NAND_BOOT = 0, + SPI_NOR_BOOT, + MMC_BOOT, + BOOT_DEV_NUM, +}; + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_PER_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, + MXC_ESDHC_CLK, + MXC_AXI_A_CLK, + MXC_AXI_B_CLK, + MXC_EMI_SLOW_CLK, + MXC_DDR_CLK +}; + +/* +enum mxc_main_clocks { + MXC_CPU_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PER_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_USB_CLK, +}; +*/ + +enum mxc_peri_clocks { + MXC_UART1_BAUD, + MXC_UART2_BAUD, + MXC_UART3_BAUD, + MXC_SSI1_BAUD, + MXC_SSI2_BAUD, + MXC_CSI_BAUD, + MXC_MSTICK1_CLK, + MXC_MSTICK2_CLK, + MXC_SPI1_CLK, + MXC_SPI2_CLK, +}; + +extern unsigned int mxc_get_clock(enum mxc_clock clk); +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); +extern enum boot_device get_boot_device(void); +extern void set_usboh3_clk(void); +extern void set_usb_phy1_clk(void); +extern void enable_usboh3_clk(unsigned char enable); +extern void enable_usb_phy1_clk(unsigned char enable); + +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_MXC_MX51_H__ */ diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/lowlevel_init.S barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/lowlevel_init.S --- barebox-2011.06.0/arch/arm/boards/vmx51/lowlevel_init.S 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/lowlevel_init.S 2011-08-16 13:58:20.771497962 +0200 @@ -0,0 +1,375 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA +*/ + +#include +#include "fslmx51.h" + +/* + * return soc version + * 0x10: TO1 + * 0x20: TO2 + * 0x30: TO3 + */ +.macro check_soc_version ret, tmp +.endm + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + ldr r1, =0x00000000 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* r3 contains the silicon rev */ + orrls r0, r0, #(1 << 25) /* disable write combine for TO 2 and lower revs */ + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ +.endm /* init_aips */ + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max +.endm /* init_max */ + +/* M4IF setup */ +.macro init_m4if + /* VPU and IPU given higher priority (0x4) + * IPU accesses with ID=0x1 given highest priority (=0xA) + */ + ldr r0, =M4IF_BASE_ADDR + + ldr r1, =0x00000203 + str r1, [r0, #0x40] + + ldr r1, =0x0 + str r1, [r0, #0x44] + + ldr r1, =0x00120125 + str r1, [r0, #0x9C] + + ldr r1, =0x001901A3 + str r1, [r0, #0x48] + +/* + ldr r1, =0x00000a01 + str r1, [r0, #0x48] + ldr r1, =0x00000404 + str r1, [r0, #0x40] +*/ +.endm /* init_m4if */ + +/* To support 133MHz DDR */ +.macro init_drive_strength +.endm /* init_drive_strength */ + +/* CPLD on CS5 setup */ +.macro init_debug_board +.endm /* init_debug_board */ + +.macro setup_pll pll, freq + ldr r2, =\pll + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + mov r1, #0x2 + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + str r3, [r2, #PLL_DP_OP] + str r3, [r2, #PLL_DP_HFS_OP] + + str r4, [r2, #PLL_DP_MFD] + str r4, [r2, #PLL_DP_HFS_MFD] + + str r5, [r2, #PLL_DP_MFN] + str r5, [r2, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] +1: ldr r1, [r2, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + ldr r1, =0x0 + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x00000300 + str r1, [r0, #CLKCTL_CCGR6] + + /* Disable IPU and HSC dividers */ + mov r1, #0x60000 + str r1, [r0, #CLKCTL_CCDR] + + /* Make sure to switch the DDR away from PLL 1 */ + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + mov r3, #DP_OP_800 + mov r4, #DP_MFD_800 + mov r5, #DP_MFN_800 + setup_pll PLL1_BASE_ADDR + + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL3_BASE_ADDR + + /* Switch peripheral to PLL 3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x000010C0 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x13239145 + str r1, [r0, #CLKCTL_CBCDR] + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL2_BASE_ADDR + + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + ldr r1, =0x000020C0 + str r1, [r0, #CLKCTL_CBCMR] + + mov r3, #DP_OP_216 + mov r4, #DP_MFD_216 + mov r5, #DP_MFN_216 + setup_pll PLL3_BASE_ADDR + + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000725 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */ + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 + movls r1, #0x1 + movhi r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1 */ + mov r1, #0 + str r1, [r0, #CLKCTL_CCSR] + + /* setup the rest */ + /* Use lp_apm (24MHz) source for perclk */ + ldr r1, =0x000020C2 + str r1, [r0, #CLKCTL_CBCMR] + /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ + ldr r1, =0x59E35100 + str r1, [r0, #CLKCTL_CBCDR] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + + /* Use PLL 2 for UART's, get 66.5MHz from it */ + ldr r1, =0xA5A2A020 + str r1, [r0, #CLKCTL_CSCMR1] + ldr r1, =0x00C30321 + str r1, [r0, #CLKCTL_CSCDR1] + + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.macro setup_wdog + ldr r0, =WDOG1_BASE_ADDR + mov r1, #0x30 + strh r1, [r0] +.endm + +.equ MX51_SRAM_BASE, 0x1ffe0000 +.equ MX51_SRAM_SIZE, 0x40000 + +.section ".text_bare_init","ax" + +.globl board_init_lowlevel +board_init_lowlevel: + + ldr r0, =MX51_SRAM_BASE + add r2, r0, #MX51_SRAM_SIZE + + /* skip device configuration ? */ + cmp pc, r0 + bls skip_device_config + cmp pc, r2 + bhi skip_device_config + + /* device configuration data */ + ldr r0, =dcd_loop + adr r1, dcd_loop + sub r4, r1, r0 /* r4 = pc relative offset */ + + ldr r0, =flash_header + add r0, r0, r4 /* r0 = pc relative flash_header */ + ldr r1, [r0,#0x20] /* dcd length */ + + ldr r0, =dcd_entry + add r0, r0, r4 /* r0 = pc relative dcd_entry */ + + add r1, r1, r0 + +dcd_loop: + ldr r2, [r0],#0x4 + ldr r2, [r0],#0x4 + ldr r3, [r0],#0x4 + str r3, [r2] + cmp r0, r1 + blt dcd_loop + +skip_device_config: + + /* check number of banks 4/8 */ + ldr r2, =0x90000000 + ldr r3, =0x83fd9000 + + mov r0, r2 /* r0 = 90000000 */ + mov r1, #0x8000000 + + str r0, [r0], r1 /* [90000000] = 0 */ + str r0, [r0], r1 /* [98000000] = 98000000 */ + + ldr r0, [r2] + ands r0, #0x8000000 + + ldr r1, [r3, #0x10] /* set banks */ + bicne r1, #0x40 + str r1, [r3, #0x10] + +#ifndef CONFIG_VMX51_ESDCS1_ENABLE + /* disable ESDCS1 */ + mov r0, #0 + str r0, [r3, #0x8] +#endif + ldr r0, =GPIO1_BASE_ADDR + ldr r1, [r0, #0x0] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x0] + ldr r1, [r0, #0x4] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x4] + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 + + init_l2cc + + init_aips + + init_max + + init_m4if + + init_drive_strength + + init_clock + + init_debug_board + + mov pc, lr + diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/Makefile barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/Makefile --- barebox-2011.06.0/arch/arm/boards/vmx51/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/Makefile 2011-06-10 13:13:22.604508183 +0200 @@ -0,0 +1,4 @@ +obj-y += lowlevel_init.o +obj-y += vmx51.o +obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o + diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/spi.c barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/spi.c --- barebox-2011.06.0/arch/arm/boards/vmx51/spi.c 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/spi.c 2011-06-10 13:13:22.604508183 +0200 @@ -0,0 +1,340 @@ +#include +#include +#include +#include +#include + +#define IMX_SPI_ACTIVE_HIGH 1 +#define SPI_RETRY_TIMES 100 +#define CLKCTL_CACRR 0x10 +#define REV_ATLAS_LITE_2_0 0x10 + +/* Only for SPI master support */ +struct imx_spi_dev { + unsigned int base; // base address of SPI module the device is connected to + unsigned int freq; // desired clock freq in Hz for this device + unsigned int ss_pol; // ss polarity: 1=active high; 0=active low + unsigned int ss; // slave select + unsigned int in_sctl; // inactive sclk ctl: 1=stay low; 0=stay high + unsigned int in_dctl; // inactive data ctl: 1=stay low; 0=stay high + unsigned int ssctl; // single burst mode vs multiple: 0=single; 1=multi + unsigned int sclkpol; // sclk polarity: active high=0; active low=1 + unsigned int sclkpha; // sclk phase: 0=phase 0; 1=phase1 + unsigned int fifo_sz; // fifo size in bytes for either tx or rx. Don't add them up! + unsigned int ctrl_reg; + unsigned int cfg_reg; +}; + +struct imx_spi_dev imx_spi_pmic = { + .base = MX51_CSPI1_BASE_ADDR, + .freq = 25000000, + .ss_pol = IMX_SPI_ACTIVE_HIGH, + .ss = 0, /* slave select 0 */ + .fifo_sz = 32, +}; + +/* + * Initialization function for a spi slave device. It must be called BEFORE + * any spi operations. The SPI module will be -disabled- after this call. + */ +static int imx_spi_init(struct imx_spi_dev *dev) +{ + unsigned int clk_src = 66500000; + unsigned int pre_div = 0, post_div = 0, i, reg_ctrl = 0, reg_config = 0; + + if (dev->freq == 0) { + printf("Error: desired clock is 0\n"); + return -1; + } + + /* control register setup */ + if (clk_src > dev->freq) { + pre_div = clk_src / dev->freq; + if (pre_div > 16) { + post_div = pre_div / 16; + pre_div = 15; + } + if (post_div != 0) { + for (i = 0; i < 16; i++) { + if ((1 << i) >= post_div) + break; + } + if (i == 16) { + printf + ("Error: no divider can meet the freq: %d\n", + dev->freq); + return -1; + } + post_div = i; + } + } + debug("pre_div = %d, post_div=%d\n", pre_div, post_div); + reg_ctrl |= pre_div << 12; + reg_ctrl |= post_div << 8; + reg_ctrl |= 1 << (dev->ss + 4); /* always set to master mode */ + + /* configuration register setup */ + reg_config |= dev->ss_pol << (dev->ss + 12); + reg_config |= dev->in_sctl << (dev->ss + 20); + reg_config |= dev->in_dctl << (dev->ss + 16); + reg_config |= dev->ssctl << (dev->ss + 8); + reg_config |= dev->sclkpol << (dev->ss + 4); + reg_config |= dev->sclkpha << (dev->ss + 0); + + debug("reg_ctrl = 0x%x\n", reg_ctrl); + /* reset the spi */ + writel(0, dev->base + 0x8); + writel(reg_ctrl, dev->base + 0x8); + debug("reg_config = 0x%x\n", reg_config); + writel(reg_config, dev->base + 0xC); + /* save control register */ + dev->cfg_reg = reg_config; + dev->ctrl_reg = reg_ctrl; + + /* clear interrupt reg */ + writel(0, dev->base + 0x10); + writel(3 << 6, dev->base + 0x18); + + return 0; +} + +static int imx_spi_xfer(struct imx_spi_dev *dev, /* spi device pointer */ + void *tx_buf, /* tx buffer (has to be 4-byte aligned) */ + void *rx_buf, /* rx buffer (has to be 4-byte aligned) */ + int burst_bits /* total number of bits in one burst (or xfer) */ + ) +{ + int val = SPI_RETRY_TIMES; + unsigned int *p_buf; + unsigned int reg; + int len, ret_val = 0; + int burst_bytes = burst_bits / 8; + + /* Account for rounding of non-byte aligned burst sizes */ + if ((burst_bits % 8) != 0) + burst_bytes++; + + if (burst_bytes > dev->fifo_sz) { + printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n", + dev->fifo_sz, burst_bytes); + return -1; + } + + dev->ctrl_reg = (dev->ctrl_reg & ~0xFFF00000) | ((burst_bits - 1) << 20); + writel(dev->ctrl_reg | 0x1, dev->base + 0x8); + writel(dev->cfg_reg, dev->base + 0xC); + debug("ctrl_reg=0x%x, cfg_reg=0x%x\n", + readl(dev->base + 0x8), readl(dev->base + 0xC)); + + /* move data to the tx fifo */ + len = burst_bytes; + for (p_buf = tx_buf; len > 0; p_buf++, len -= 4) + writel(*p_buf, dev->base + 0x4); + + reg = readl(dev->base + 0x8); + reg |= (1 << 2); /* set xch bit */ + writel(reg, dev->base + 0x8); + + /* poll on the TC bit (transfer complete) */ + while ((val-- > 0) && (readl(dev->base + 0x18) & (1 << 7)) == 0); + + /* clear the TC bit */ + writel(3 << 6, dev->base + 0x18); + + if (val == 0) { + printf("Error: re-tried %d times without response. Give up\n", + SPI_RETRY_TIMES); + ret_val = -1; + goto error; + } + + /* move data in the rx buf */ + len = burst_bytes; + for (p_buf = rx_buf; len > 0; p_buf++, len -= 4) + *p_buf = readl(dev->base + 0x0); + +error: + writel(0, dev->base + 0x8); + return ret_val; +} + +/* + * To read/write to a PMIC register. For write, it does another read for the + * actual register value. + * + * @param reg register number inside the PMIC + * @param val data to be written to the register; don't care for read + * @param write 0 for read; 1 for write + * + * @return the actual data in the PMIC register + */ +static unsigned int +pmic_reg(unsigned int reg, unsigned int val, unsigned int write) +{ + static unsigned int pmic_tx, pmic_rx; + + if (reg > 63 || write > 1) { + printf(" = %d is invalid. Should be less then 63\n", + reg); + return 0; + } + pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); + debug("reg=0x%x, val=0x%08x\n", reg, pmic_tx); + + imx_spi_xfer(&imx_spi_pmic, (unsigned char *) &pmic_tx, + (unsigned char *) &pmic_rx, (4 * 8)); + + if (write) { + pmic_tx &= ~(1 << 31); + imx_spi_xfer(&imx_spi_pmic, (unsigned char *) &pmic_tx, + (unsigned char *) &pmic_rx, (4 * 8)); + } + + return pmic_rx; +} + +static void show_pmic_info(void) +{ + unsigned int rev_id; + char *rev; + + rev_id = pmic_reg(7, 0, 0); + + switch (rev_id & 0x1F) { + case 0x1: rev = "1.0"; break; + case 0x9: rev = "1.1"; break; + case 0xa: rev = "1.2"; break; + case 0x10: + if (((rev_id >> 9) & 0x3) == 0) + rev = "2.0"; + else + rev = "2.0a"; + break; + case 0x11: rev = "2.1"; break; + case 0x18: rev = "3.0"; break; + case 0x19: rev = "3.1"; break; + case 0x1a: rev = "3.2"; break; + case 0x2: rev = "3.2a"; break; + case 0x1b: rev = "3.3"; break; + case 0x1d: rev = "3.5"; break; + default: rev = "unknown"; break; + } + + printf("PMIC ID: 0x%08x [Rev: %s]\n", rev_id, rev); +} + +int babbage_power_init(void) +{ + unsigned int val; + unsigned int reg; + + imx_spi_init(&imx_spi_pmic); + + show_pmic_info(); + + /* Write needed to Power Gate 2 register */ + val = pmic_reg(34, 0, 0); + val &= ~0x10000; + pmic_reg(34, val, 1); + + /* Write needed to update Charger 0 */ + pmic_reg(48, 0x0023807F, 1); + + /* power up the system first */ + pmic_reg(34, 0x00200000, 1); + + if (1) { + /* Set core voltage to 1.1V */ + val = pmic_reg(24, 0, 0); + val &= ~0x1f; + val |= 0x14; + pmic_reg(24, val, 1); + + /* Setup VCC (SW2) to 1.25 */ + val = pmic_reg(25, 0, 0); + val &= ~0x1f; + val |= 0x1a; + pmic_reg(25, val, 1); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + val = pmic_reg(26, 0, 0); + val &= ~0x1f; + val |= 0x1a; + pmic_reg(26, val, 1); + udelay(50); + /* Raise the core frequency to 800MHz */ + writel(0x0, MX51_CCM_BASE_ADDR + CLKCTL_CACRR); + } else { + /* TO 3.0 */ + /* Setup VCC (SW2) to 1.225 */ + val = pmic_reg(25, 0, 0); + val &= ~0x1f; + val |= 0x19; + pmic_reg(25, val, 1); + + /* Setup 1V2_DIG1 (SW3) to 1.2 */ + val = pmic_reg(26, 0, 0); + val &= ~0x1f; + val |= 0x18; + pmic_reg(26, val, 1); + } + + if (((pmic_reg(7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) + || (((pmic_reg(7, 0, 0) >> 9) & 0x3) == 0)) { + /* Set switchers in PWM mode for Atlas 2.0 and lower */ + /* Setup the switcher mode for SW1 & SW2 */ + val = pmic_reg(28, 0, 0); + val &= ~0x3c0f; + val |= 0x1405; + pmic_reg(28, val, 1); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg(29, 0, 0); + val &= ~0xf0f; + val |= 0x505; + pmic_reg(29, val, 1); + } else { + /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ + /* Setup the switcher mode for SW1 & SW2 */ + val = pmic_reg(28, 0, 0); + val &= ~0x3c0f; + val |= 0x2008; + pmic_reg(28, val, 1); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg(29, 0, 0); + val &= ~0xf0f; + val |= 0x808; + pmic_reg(29, val, 1); + } + + /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ + val = pmic_reg(30, 0, 0); + val &= ~0x34030; + val |= 0x10020; + pmic_reg(30, val, 1); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + val = pmic_reg(31, 0, 0); + val &= ~0x1FC; + val |= 0x1F4; + pmic_reg(31, val, 1); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = 0x208; + pmic_reg(33, val, 1); + udelay(200); + + gpio_direction_output(32 + 14, 0); /* Lower reset line */ + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = 0x49249; + pmic_reg(33, val, 1); + + udelay(500); + + gpio_set_value(32 + 14, 1); + + return 0; +} + diff -urN barebox-2011.06.0/arch/arm/boards/vmx51/vmx51.c barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/vmx51.c --- barebox-2011.06.0/arch/arm/boards/vmx51/vmx51.c 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/boards/vmx51/vmx51.c 2011-08-16 13:59:25.690247276 +0200 @@ -0,0 +1,537 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static struct memory_platform_data sdram0_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram0_dev = { + .id = -1, + .name = "mem", + .map_base = 0x90000000, +// .size = 512 * 1024 * 1024, + .size = 128 * 1024 * 1024, + .platform_data = &sdram0_pdata, +}; + +static struct memory_platform_data sdram1_pdata = { + .name = "ram1", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram1_dev = { + .id = -1, + .name = "mem", + .map_base = 0xa0000000, + .size = 128 * 1024 * 1024, + .platform_data = &sdram1_pdata, +}; + +static struct memory_platform_data sram0_pdata = { + .name = "sram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sram0_dev = { + .id = -1, + .name = "mem", + .map_base = 0x1ffe0000, +// .size = 128 * 1024, + .size = 256 * 1024, + .platform_data = &sram0_pdata, +}; +/* +static struct memory_platform_data sram1_pdata = { + .name = "sram1", + .flags = DEVFS_RDWR, +}; + +static struct device_d sram1_dev = { + .id = -1, + .name = "mem", + .map_base = 0x20000000, + .size = 128 * 1024, + .platform_data = &sram1_pdata, +}; +*/ +#ifdef CONFIG_DRIVER_NET_FEC_IMX +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 0x1F, +}; +#endif +#ifdef CONFIG_I2C_IMX +static struct i2c_board_info i2c_devices[] = { +#ifdef CONFIG_I2C_MC13892 + { + I2C_BOARD_INFO("mc13892-i2c", 0x08), + }, +#endif +}; +#endif +#ifdef CONFIG_NAND_IMX +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = IMX_NFC_BASE, + .platform_data = &nand_info, +}; +#endif +#ifdef CONFIG_LED_GPIO +// LGPIO0 = GPIO2_4 +static struct gpio_led led0red = { + .led.name = "red", + .gpio = 1 * 32 + 4, + .active_low = 0, +}; + +// LGPIO1 = GPIO2_5 +static struct gpio_led led1orange = { + .led.name = "orange", + .gpio = 1 * 32 + 5, + .active_low = 0, +}; +#endif +// PAD_CTRL_OFFS, MUX_CTRL_OFFS, MUX_MODE, SELECT_INPUT_OFFS, SELECT_INPUT, PAD_CTRL +#define MX51_PAD_EIM_D16__I2C1_DAT IOMUX_PAD(0x3F0, 0x5C, 0x14, 0x0, 0, 0x10D) // I2C1_DAT +#define MX51_PAD_EIM_D19__I2C1_CLK IOMUX_PAD(0x3FC, 0x68, 0x14, 0x0, 0, 0x10D) // I2C1_CLK + +#define MX51_PAD_EIM_D24__I2C2_DAT IOMUX_PAD(0x410, 0x7C, 0x14, 0x0, 0, 0x10D) // I2C2_DAT +#define MX51_PAD_EIM_D27__I2C2_CLK IOMUX_PAD(0x41C, 0x88, 0x14, 0x0, 0, 0x10D) // I2C2_CLK + +#define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) // FEC_RST +#define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) // CKIH1_EN + +#define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) // GPIO2_4 = LGPIO0 +#define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0, 0, NO_PAD_CTRL) // GPIO2_5 = LGPIO1 + +#define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) // GPIO4_24 +#define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) // GPIO4_25 + +static struct pad_desc vmx51_iomux_pads[] = { + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +#ifdef CONFIG_DRIVER_NET_FEC_IMX + MX51_PAD_EIM_EB2__FEC_MDIO, + MX51_PAD_EIM_EB3__FEC_RDATA1, + MX51_PAD_EIM_CS2__FEC_RDATA2, + MX51_PAD_EIM_CS3__FEC_RDATA3, + MX51_PAD_EIM_CS4__FEC_RX_ER, + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_NANDF_RB2__FEC_COL, + MX51_PAD_NANDF_RB3__FEC_RX_CLK, + MX51_PAD_NANDF_RB7__FEC_TX_ER, + MX51_PAD_NANDF_CS3__FEC_MDC, + MX51_PAD_NANDF_CS4__FEC_TDATA1, + MX51_PAD_NANDF_CS5__FEC_TDATA2, + MX51_PAD_NANDF_CS6__FEC_TDATA3, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + MX51_PAD_NANDF_D11__FEC_RX_DV, + MX51_PAD_NANDF_RB6__FEC_RDATA0, + MX51_PAD_NANDF_D8__FEC_TDATA0, +#endif +#ifdef CONFIG_I2C_IMX + MX51_PAD_EIM_D16__I2C1_DAT, + MX51_PAD_EIM_D19__I2C1_CLK, + MX51_PAD_EIM_D24__I2C2_DAT, + MX51_PAD_EIM_D27__I2C2_CLK, +#endif +#ifdef CONFIG_DRIVER_SPI_IMX +// MX51_PAD_CSPI1_SS0__CSPI1_SS0, +// MX51_PAD_CSPI1_SS1__CSPI1_SS1, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_CSPI1_MOSI__CSPI1_MOSI, + MX51_PAD_CSPI1_MISO__CSPI1_MISO, + MX51_PAD_CSPI1_RDY__CSPI1_RDY, + MX51_PAD_CSPI1_SCLK__CSPI1_SCLK, +#endif +#if CONFIG_LED_GPIO + MX51_PAD_EIM_D20__GPIO2_4, + MX51_PAD_EIM_D21__GPIO2_5, +#endif +}; + +#ifdef CONFIG_MMU +static void vmx51_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0x90000000, 0x90000000, 512, PMD_SECT_DEF_CACHED); + arm_create_section(0xb0000000, 0x90000000, 512, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x20000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + + mmu_enable(); +} +#else +static void vmx51_mmu_init(void) +{ +} +#endif + +#define IMX_ESD_BASE 0x83fd9000 + +static void vmx51_sdram_init(void) +{ + uchar rows, cols, dsiz, banks; + uint32_t size, esdctl, esdmsc; + + esdctl = readl(IMX_ESD_BASE); + esdmsc = readl(IMX_ESD_BASE+0x10); + + rows = ((esdctl >> 24) & 7); + cols = ((esdctl >> 20) & 3); + dsiz = ((esdctl >> 17) & 1); // 0=16bit, 1=32bit + banks = ((esdmsc >> 6) & 1); // 0=4banks, 1=8banks + size = (esdctl)? 1 << (rows + cols + banks + dsiz + 22) : 0; + + sdram0_dev.size = size; + + printk("SDRAM at 0x%08x: %dMB (DDR2 2x%dMb, %d ROWs, %d COLs, %d BANKs)\n", + sdram0_dev.map_base, size >> 20, size >> 18, rows + 11, cols + 8, 4 << banks); + + esdctl = readl(IMX_ESD_BASE + 0x08); + rows = ((esdctl >> 24) & 7); + cols = ((esdctl >> 20) & 3); + dsiz = ((esdctl >> 17) & 1); // 0=16bit, 1=32bit + size = (esdctl)? 1 << (rows + cols + banks + dsiz + 22) : 0; + + sdram1_dev.size = size; + + printk("SDRAM at 0x%08x: %dMB (DDR2 2x%dMb, %d ROWs, %d COLs, %d BANKs)\n", + sdram1_dev.map_base, size >> 20, size >> 18, rows + 11, cols + 8, 4 << banks); +} + +#ifdef CONFIG_DRIVER_SPI_IMX + +#define VMX51_ECSPI1_CS0 (3 * 32 + 24) // GPIO4_24 +#define VMX51_ECSPI1_CS1 (3 * 32 + 25) // GPIO4_25 + +static int spi_0_cs[] = { VMX51_ECSPI1_CS0 , VMX51_ECSPI1_CS1 }; + +static struct spi_imx_master spi_0_data = { + .chipselect = spi_0_cs, + .num_chipselect = ARRAY_SIZE(spi_0_cs), +}; + +static const struct spi_board_info mx51_spi_board_info[] = { + { +// .name = "mc13892-spi", + .name = "flash-spi", + .max_speed_hz = 300000, + .bus_num = 0, + .chip_select = 1, + }, +}; +#endif + +#define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x5DC, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) // FEC_RXD0 +#define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46C, 0x0D8, 1, 0x0, 0, NO_PAD_CTRL) // FEC_RXD1 +#define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47C, 0x0E8, 1, 0x0, 0, NO_PAD_CTRL) // FEC_RXD2 +#define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0EC, 1, 0x0, 0, NO_PAD_CTRL) // INTSEL + +#define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0F0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0F4, 1, 0x0, 0, NO_PAD_CTRL) + +#define GPIO_LAN8700_RESET (2 * 32 + 30) // GPIO3_30 + +#define MX51_CCM_CACRR 0x10 + +static void imx51_power_init(void) +{ + struct pad_desc fec_gpio_pads[] = { + MX51_PAD_NANDF_D10__GPIO3_30, // FEC_RESET_B + MX51_PAD_NANDF_D9__GPIO3_31, // MODE0 + MX51_PAD_EIM_EB3__GPIO2_23, // MODE1 + MX51_PAD_EIM_CS2__GPIO2_27, // MODE2 + MX51_PAD_EIM_CS3__GPIO2_28, // INTSEL + MX51_PAD_NANDF_D11__GPIO3_29, + MX51_PAD_NANDF_RB3__GPIO3_11, // REGOFF + MX51_PAD_EIM_CS4__GPIO2_29, + MX51_PAD_NANDF_RB2__GPIO3_10, // RMII + MX51_PAD_EIM_CS5__GPIO2_30, // PHYAD4 + }; + + struct pad_desc fec_restore_pads[] = { + MX51_PAD_NANDF_RB6__FEC_RDATA0, + MX51_PAD_EIM_EB3__FEC_RDATA1, + MX51_PAD_EIM_CS2__FEC_RDATA2, + MX51_PAD_EIM_CS3__FEC_RDATA3, + MX51_PAD_NANDF_D11__FEC_RX_DV, + MX51_PAD_NANDF_RB3__FEC_RX_CLK, + MX51_PAD_EIM_CS4__FEC_RX_ER, + MX51_PAD_NANDF_RB2__FEC_COL, + MX51_PAD_EIM_CS5__FEC_CRS, + }; + + struct mc13892 *mc13892; + u32 val; + + mc13892 = mc13892_get(); + if (!mc13892) { + printf("could not get mc13892\n"); + return; + } + /* Write needed to update Charger 0 */ + mc13892_reg_write(mc13892, 48, 0x0023807F); + + if (imx_silicon_revision() < MX51_CHIP_REV_3_0) { + /* Set core voltage to 1.1V */ + mc13892_reg_read(mc13892, 24, &val); + val &= ~0x1f; + val |= 0x14; + mc13892_reg_write(mc13892, 24, val); + + /* Setup VCC (SW2) to 1.25 */ + mc13892_reg_read(mc13892, 25, &val); + val &= ~0x1f; + val |= 0x1a; + mc13892_reg_write(mc13892, 25, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + mc13892_reg_read(mc13892, 26, &val); + val &= ~0x1f; + val |= 0x1a; + mc13892_reg_write(mc13892, 26, val); + udelay(50); + /* Raise the core frequency to 800MHz */ + writel(0x0, MX51_CCM_BASE_ADDR + MX51_CCM_CACRR); + } else { + /* Setup VCC (SW2) to 1.225 */ + mc13892_reg_read(mc13892, 25, &val); + val &= ~0x1f; + val |= 0x19; + mc13892_reg_write(mc13892, 25, val); + + /* Setup 1V2_DIG1 (SW3) to 1.2 */ + mc13892_reg_read(mc13892, 26, &val); + val &= ~0x1f; + val |= 0x18; + mc13892_reg_write(mc13892, 26, val); + } + + if (mc13892_get_revision(mc13892) < MC13892_REVISION_2_0) { + /* Set switchers in PWM mode for Atlas 2.0 and lower */ + /* Setup the switcher mode for SW1 & SW2*/ + mc13892_reg_read(mc13892, 28, &val); + val &= ~0x3c0f; + val |= 0x1405; + mc13892_reg_write(mc13892, 28, val); + + /* Setup the switcher mode for SW3 & SW4 */ + mc13892_reg_read(mc13892, 29, &val); + val &= ~0xf0f; + val |= 0x505; + mc13892_reg_write(mc13892, 29, val); + } else { + /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ + /* Setup the switcher mode for SW1 & SW2*/ + mc13892_reg_read(mc13892, 28, &val); + val &= ~0x3c0f; + val |= 0x2008; + mc13892_reg_write(mc13892, 28, val); + + /* Setup the switcher mode for SW3 & SW4 */ + mc13892_reg_read(mc13892, 29, &val); + val &= ~0xf0f; + val |= 0x808; + mc13892_reg_write(mc13892, 29, val); + } + /* Turn off VGEN1 (FEC) */ + mc13892_reg_read(mc13892, 32, &val); + val &= ~0x01; + mc13892_reg_write(mc13892, 32, val); + + /* Set VGEN1 to 3.15V */ + mc13892_reg_read(mc13892, 30, &val); + val |= 0x03; + mc13892_reg_write(mc13892, 30, val); + +#ifdef CONFIG_DRIVER_NET_FEC_IMX + mxc_iomux_v3_setup_multiple_pads(fec_gpio_pads, + ARRAY_SIZE(fec_gpio_pads)); + + // assert PHY reset + gpio_direction_output(GPIO_LAN8700_RESET, 0); // GPIO3_30 + + mdelay(5); + + // Turn on VGEN1 (FEC) + mc13892_reg_read(mc13892, 32, &val); + val |= 0x01; + mc13892_reg_write(mc13892, 32, val); + + mdelay(10); + + // set PHY mode pins to 1 + gpio_direction_output(95, 1); // GPIO3_31 = MODE0 = 1 + gpio_direction_output(55, 1); // GPIO2_23 = MODE1 = 1 + gpio_direction_output(59, 1); // GPIO2_27 = MODE2 = 1 + + gpio_direction_output(60, 0); // GPIO2_28 = INTSEL = 0 + + gpio_direction_output(93, 0); // GPIO3_29 = 0 + gpio_direction_output(75, 0); // GPIO3_11 = REGOFF = 0 + gpio_direction_output(61, 0); // GPIO2_29 = 0 + + gpio_direction_output(74, 0); // GPIO3_10 = RMII = 0 + gpio_direction_output(62, 1); // GPIO2_30 = PHYAD4 = 1 + + mdelay(22); + + // deassert PHY reset + gpio_set_value(GPIO_LAN8700_RESET, 1); + + mdelay(5); + + mxc_iomux_v3_setup_multiple_pads(fec_restore_pads, + ARRAY_SIZE(fec_restore_pads)); +#endif + /* Enable GPO2,GPO3 */ + mc13892_reg_read(mc13892, 34, &val); + val |= 0x0500; + mc13892_reg_write(mc13892, 34, val); +} + +static int vmx51_devices_init(void) +{ + vmx51_sdram_init(); + + vmx51_mmu_init(); + +#ifdef CONFIG_LED_GPIO + led_gpio_register(&led0red); + led_gpio_register(&led1orange); +#endif +#ifdef CONFIG_DRIVER_NET_FEC_IMX + imx51_add_fec(&fec_info); +#endif +#ifdef CONFIG_MCI_IMX_ESDHC + imx51_add_mmc0(NULL); + imx51_add_mmc1(NULL); +#endif +#ifdef CONFIG_DRIVER_SPI_IMX + spi_register_board_info(mx51_spi_board_info, + ARRAY_SIZE(mx51_spi_board_info)); + imx51_add_spi0(&spi_0_data); +#endif +#ifdef CONFIG_I2C_IMX + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + imx51_add_i2c0(NULL); + imx51_add_i2c1(NULL); +#endif + imx51_power_init(); +#ifdef CONFIG_NAND_IMX + register_device(&nand_dev); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); +#endif + if( sdram0_dev.size) + register_device(&sdram0_dev); + + if( sdram1_dev.size) + register_device(&sdram1_dev); + + register_device(&sram0_dev); +// register_device(&sram1_dev); + + armlinux_add_dram(&sdram0_dev); + armlinux_add_dram(&sdram1_dev); + + armlinux_set_bootparams((void *)0x90000100); + armlinux_set_revision(0x51000|imx_silicon_revision()); + armlinux_set_architecture(MACH_TYPE_VMX51); + + return 0; +} + +device_initcall(vmx51_devices_init); +#if 0 +static int f3s_part_init(void) +{ + devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); + + return 0; +} +late_initcall(f3s_part_init); +#endif +static int vmx51_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads( vmx51_iomux_pads, + ARRAY_SIZE(vmx51_iomux_pads)); + + imx51_add_uart0(); + + return 0; +} + +console_initcall(vmx51_console_init); + diff -urN barebox-2011.06.0/arch/arm/configs/voipac_vmx51_defconfig barebox-2011.06.0-vmx51/arch/arm/configs/voipac_vmx51_defconfig --- barebox-2011.06.0/arch/arm/configs/voipac_vmx51_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2011.06.0-vmx51/arch/arm/configs/voipac_vmx51_defconfig 2011-08-16 13:48:58.020244380 +0200 @@ -0,0 +1,331 @@ +# +# Automatically generated make config: don't edit +# Linux/arm 2011.06.0 Barebox Configuration +# Mon Aug 15 18:37:46 2011 +# +# CONFIG_BOARD_LINKER_SCRIPT is not set +CONFIG_GENERIC_LINKER_SCRIPT=y +CONFIG_ARM=y +CONFIG_ARM_LINUX=y + +# +# System Type +# +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_EP93XX is not set +CONFIG_ARCH_IMX=y +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_S3C24xx is not set +# CONFIG_ARCH_VERSATILE is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y + +# +# processor features +# +# CONFIG_BOOT_ENDIANNESS_SWITCH is not set +CONFIG_ARCH_TEXT_BASE=0x97f00000 +CONFIG_BOARDINFO="Voipac VMX51" +CONFIG_ARCH_IMX_INTERNAL_BOOT=y +CONFIG_ARCH_IMX_INTERNAL_BOOT_NAND=y +# CONFIG_ARCH_IMX_INTERNAL_BOOT_NOR is not set +# CONFIG_ARCH_IMX_INTERNAL_BOOT_ONENAND is not set + +# +# Freescale i.MX System-on-Chip +# +# CONFIG_ARCH_IMX1 is not set +# CONFIG_ARCH_IMX21 is not set +# CONFIG_ARCH_IMX25 is not set +# CONFIG_ARCH_IMX27 is not set +# CONFIG_ARCH_IMX31 is not set +# CONFIG_ARCH_IMX35 is not set +CONFIG_ARCH_IMX51=y +CONFIG_MACH_VMX51=y +# CONFIG_MACH_FREESCALE_MX51_PDK is not set +# CONFIG_MACH_EUKREA_CPUIMX51SD is not set + +# +# Board specific settings +# +# CONFIG_VMX51_ESDCS1_ENABLE is not set + +# +# i.MX specific settings +# +CONFIG_AEABI=y + +# +# Arm specific settings +# +CONFIG_CMD_ARM_CPUINFO=y +# CONFIG_CPU_V7_DCACHE_SKIP is not set +# CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS is not set +CONFIG_ARM_EXCEPTIONS=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG" +CONFIG_HAS_KALLSYMS=y +CONFIG_HAS_MODULES=y +CONFIG_CMD_MEMORY=y +CONFIG_ENV_HANDLING=y +CONFIG_GENERIC_GPIO=y +CONFIG_BLOCK=y + +# +# General Settings +# +CONFIG_LOCALVERSION_AUTO=y +CONFIG_ENVIRONMENT_VARIABLES=y + +# +# memory layout +# +CONFIG_HAVE_MMU=y +# CONFIG_MMU is not set +CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y +CONFIG_TEXT_BASE=0x97f00000 +CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y +CONFIG_MEMORY_LAYOUT_DEFAULT=y +# CONFIG_MEMORY_LAYOUT_FIXED is not set +CONFIG_STACK_SIZE=0x8000 +CONFIG_MALLOC_SIZE=0x800000 +# CONFIG_BROKEN is not set +# CONFIG_EXPERIMENTAL is not set +CONFIG_MALLOC_DLMALLOC=y +# CONFIG_KALLSYMS is not set +CONFIG_MACH_HAS_LOWLEVEL_INIT=y +CONFIG_MACH_DO_LOWLEVEL_INIT=y +CONFIG_PROMPT="barebox:" +CONFIG_BAUDRATE=115200 +CONFIG_LONGHELP=y +CONFIG_CBSIZE=1024 +CONFIG_MAXARGS=16 +CONFIG_SHELL_HUSH=y +# CONFIG_SHELL_SIMPLE is not set +CONFIG_GLOB=y +CONFIG_PROMPT_HUSH_PS2="> " +# CONFIG_HUSH_FANCY_PROMPT is not set +# CONFIG_HUSH_GETOPT is not set +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_MENU is not set +# CONFIG_PASSWORD is not set +CONFIG_DYNAMIC_CRC_TABLE=y +CONFIG_ERRNO_MESSAGES=y +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_FULL=y +CONFIG_CONSOLE_ACTIVATE_FIRST=y +# CONFIG_OF_FLAT_TREE is not set +# CONFIG_PARTITION is not set +CONFIG_DEFAULT_ENVIRONMENT=y +# CONFIG_DEFAULT_ENVIRONMENT_GENERIC is not set +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/vmx51/env" +CONFIG_POLLER=y + +# +# Debugging +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_FLASH_NOISE is not set +# CONFIG_ENABLE_PARTITION_NOISE is not set +# CONFIG_ENABLE_DEVICE_NOISE is not set +CONFIG_COMMAND_SUPPORT=y + +# +# commands +# + +# +# scripting +# +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TRUE=y +CONFIG_CMD_FALSE=y +# CONFIG_CMD_LOGIN is not set +# CONFIG_CMD_PASSWD is not set + +# +# file commands +# +CONFIG_CMD_LS=y +CONFIG_CMD_RM=y +CONFIG_CMD_CAT=y +CONFIG_CMD_MKDIR=y +CONFIG_CMD_RMDIR=y +CONFIG_CMD_CP=y +CONFIG_CMD_PWD=y +CONFIG_CMD_CD=y +CONFIG_CMD_MOUNT=y +CONFIG_CMD_UMOUNT=y +CONFIG_CMD_NAND=y + +# +# console +# +CONFIG_CMD_CLEAR=y +CONFIG_CMD_ECHO=y +# CONFIG_CMD_ECHO_E is not set + +# +# memory +# +# CONFIG_CMD_LOADB is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_CRC is not set +CONFIG_CMD_MTEST=y +# CONFIG_CMD_MTEST_ALTERNATIVE is not set + +# +# flash +# +CONFIG_CMD_FLASH=y +# CONFIG_CMD_UBI is not set + +# +# booting +# +# CONFIG_CMD_BOOTM is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_TEST=y +CONFIG_CMD_VERSION=y +CONFIG_CMD_HELP=y +CONFIG_CMD_DEVINFO=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_UNLZO is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +# CONFIG_NET_NFS is not set +CONFIG_NET_PING=y +CONFIG_NET_TFTP=y +# CONFIG_NET_TFTP_PUSH is not set +# CONFIG_NET_NETCONSOLE is not set +# CONFIG_NET_RESOLV is not set + +# +# Drivers +# + +# +# serial drivers +# +# CONFIG_DRIVER_SERIAL_ARM_DCC is not set +CONFIG_DRIVER_SERIAL_IMX=y +# CONFIG_DRIVER_SERIAL_NS16550 is not set +CONFIG_ARCH_HAS_FEC_IMX=y +CONFIG_MIIDEV=y + +# +# Network drivers +# +# CONFIG_DRIVER_NET_SMC911X is not set +# CONFIG_DRIVER_NET_SMC91111 is not set +CONFIG_DRIVER_NET_FEC_IMX=y + +# +# SPI drivers +# +# CONFIG_SPI is not set +CONFIG_DRIVER_SPI_IMX_2_3=y +CONFIG_I2C=y + +# +# I2C Hardware Bus support +# +CONFIG_I2C_IMX=y + +# +# flash drivers +# +# CONFIG_DRIVER_CFI is not set +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_WRITE=y +CONFIG_NAND_ECC_SOFT=y +CONFIG_NAND_ECC_HW=y +CONFIG_NAND_ECC_HW_SYNDROME=y +CONFIG_NAND_ECC_HW_NONE=y +CONFIG_NAND_INFO=y +CONFIG_NAND_BBT=y +CONFIG_NAND_READ_OOB=y +CONFIG_NAND_IMX=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_UBI is not set +CONFIG_ATA=y + +# +# drive types +# +# CONFIG_ATA_WRITE is not set +CONFIG_ATA_DISK=y + +# +# interface types +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set +# CONFIG_VIDEO is not set +CONFIG_MCI=y + +# +# --- Feature list --- +# +# CONFIG_MCI_STARTUP is not set +CONFIG_MCI_INFO=y +# CONFIG_MCI_WRITE is not set + +# +# --- MCI host drivers --- +# +CONFIG_MCI_IMX_ESDHC=y +# CONFIG_MCI_IMX_ESDHC_PIO is not set + +# +# MFD +# +CONFIG_I2C_MC13892=y +# CONFIG_I2C_MC34704 is not set +# CONFIG_I2C_MC9SDZ60 is not set +# CONFIG_I2C_LP3972 is not set +# CONFIG_I2C_TWL4030 is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y +# CONFIG_LED_GPIO_RGB is not set +CONFIG_LED_TRIGGERS=y + +# +# Filesystem support +# +# CONFIG_FS_CRAMFS is not set +CONFIG_FS_RAMFS=y +CONFIG_FS_DEVFS=y +CONFIG_FS_FAT=y +# CONFIG_FS_FAT_WRITE is not set +CONFIG_FS_FAT_LFN=y +CONFIG_CRC32=y +# CONFIG_DIGEST is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +# CONFIG_PROCESS_ESCAPE_SEQUENCE is not set diff -urN barebox-2011.06.0/arch/arm/mach-imx/imx51.c barebox-2011.06.0-vmx51/arch/arm/mach-imx/imx51.c --- barebox-2011.06.0/arch/arm/mach-imx/imx51.c 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/arch/arm/mach-imx/imx51.c 2011-06-10 13:38:49.455755404 +0200 @@ -35,6 +35,8 @@ static u32 mx51_silicon_revision; static char *mx51_rev_string = "unknown"; +static char *mx51_reset_source = "unknown"; +static char *mx51_boot_device = "unknown"; int imx_silicon_revision(void) { @@ -70,11 +72,68 @@ return 0; } + +static int query_reset_source(void) +{ + void __iomem *rom = (void *) MX51_SRC_BASE_ADDR; + u32 rst; + + rst = readl(rom + 0x8); + switch (rst) { + case 0x0001: + mx51_reset_source = "POR"; + break; + case 0x0009: + mx51_reset_source = "RST"; + break; + case 0x0010: + case 0x0011: + mx51_reset_source = "WDOG"; + break; + } + return 0; +} + +#define MX51_IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ +#define NAND_FLASH_BOOT 0x10000000 +#define SPI_NOR_FLASH_BOOT 0x80000000 +#define MMC_FLASH_BOOT 0x40000000 + +static int query_boot_device(void) +{ + void __iomem *rom = (void *) MX51_SRC_BASE_ADDR; + + u32 soc_sbmr = readl(rom + 0x4); + u32 bt_mem_ctl = soc_sbmr & 0x00000003; + + switch (bt_mem_ctl) { + case 0x3: { + u32 bt_mem_type = (soc_sbmr & 0x00000180) >> 7; + + switch(bt_mem_type) { + case 0: + mx51_boot_device = "MMC"; + case 3: + mx51_boot_device = "SPI"; + } + } break; + case 0x1: + mx51_boot_device = "NAND"; + break; + } + return 0; +} + core_initcall(query_silicon_revision); +core_initcall(query_reset_source); +core_initcall(query_boot_device); static int imx51_print_silicon_rev(void) { - printf("detected i.MX51 rev %s\n", mx51_rev_string); + printf("Detected CPU i.MX51 rev %s [%s]\n", + mx51_rev_string, mx51_reset_source); + + printf("Boot device: %s\n", mx51_boot_device); return 0; } diff -urN barebox-2011.06.0/arch/arm/mach-imx/include/mach/devices-imx51.h barebox-2011.06.0-vmx51/arch/arm/mach-imx/include/mach/devices-imx51.h --- barebox-2011.06.0/arch/arm/mach-imx/include/mach/devices-imx51.h 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/arch/arm/mach-imx/include/mach/devices-imx51.h 2011-06-10 13:13:22.643417738 +0200 @@ -48,7 +48,7 @@ static inline struct device_d *imx51_add_mmc1(void *pdata) { - return imx_add_esdhc((void *)MX51_MMC_SDHC2_BASE_ADDR, 0, pdata); + return imx_add_esdhc((void *)MX51_MMC_SDHC2_BASE_ADDR, 1, pdata); } static inline struct device_d *imx51_add_nand(struct imx_nand_platform_data *pdata) diff -urN barebox-2011.06.0/arch/arm/mach-imx/include/mach/imx51-regs.h barebox-2011.06.0-vmx51/arch/arm/mach-imx/include/mach/imx51-regs.h --- barebox-2011.06.0/arch/arm/mach-imx/include/mach/imx51-regs.h 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/arch/arm/mach-imx/include/mach/imx51-regs.h 2011-06-10 13:13:22.654509441 +0200 @@ -105,6 +105,7 @@ #define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) #define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 +#define IMX_NFC_BASE MX51_NFC_AXI_BASE_ADDR /* * Memory regions and CS diff -urN barebox-2011.06.0/arch/arm/mach-imx/Kconfig barebox-2011.06.0-vmx51/arch/arm/mach-imx/Kconfig --- barebox-2011.06.0/arch/arm/mach-imx/Kconfig 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/arch/arm/mach-imx/Kconfig 2011-08-15 17:59:55.529194081 +0200 @@ -2,6 +2,7 @@ config ARCH_TEXT_BASE hex + default 0x97f00000 if MACH_VMX51 default 0x83f00000 if MACH_EUKREA_CPUIMX25 default 0xa0000000 if MACH_EUKREA_CPUIMX27 default 0x87f00000 if MACH_EUKREA_CPUIMX35 @@ -23,6 +24,7 @@ default 0x93d00000 if MACH_TX25 config BOARDINFO + default "Voipac VMX51" if MACH_VMX51 default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25 default "Eukrea CPUIMX27" if MACH_EUKREA_CPUIMX27 default "Eukrea CPUIMX35" if MACH_EUKREA_CPUIMX35 @@ -380,6 +382,14 @@ prompt "i.MX51 Board Type" +config MACH_VMX51 + bool "Voipac VMX51" + select HAVE_MMU + select MACH_HAS_LOWLEVEL_INIT + help + Say Y here if you are using the Voipac Technologies VMX51 module + equipped with a Freescale i.MX51 Processor + config MACH_FREESCALE_MX51_PDK bool "Freescale i.MX51 PDK" select HAVE_MMU @@ -399,6 +409,11 @@ menu "Board specific settings " +if MACH_VMX51 + config VMX51_ESDCS1_ENABLE + bool "Enable second VMX51 DDR2 bank" +endif + if MACH_PCM043 choice prompt "Display type" diff -urN barebox-2011.06.0/arch/arm/mach-imx/speed-imx51.c barebox-2011.06.0-vmx51/arch/arm/mach-imx/speed-imx51.c --- barebox-2011.06.0/arch/arm/mach-imx/speed-imx51.c 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/arch/arm/mach-imx/speed-imx51.c 2011-06-10 13:13:22.654509441 +0200 @@ -156,6 +156,11 @@ return imx_get_ipgclk(); } +ulong imx_get_i2cclk(void) +{ + return imx_get_ipgclk(); +} + unsigned long imx_get_mmcclk(void) { u32 reg, prediv, podf, rate; diff -urN barebox-2011.06.0/arch/arm/Makefile barebox-2011.06.0-vmx51/arch/arm/Makefile --- barebox-2011.06.0/arch/arm/Makefile 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/arch/arm/Makefile 2011-06-10 13:13:22.654509441 +0200 @@ -55,6 +55,7 @@ # Board directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +board-$(CONFIG_MACH_VMX51) := vmx51 board-$(CONFIG_MACH_A9M2410) := a9m2410 board-$(CONFIG_MACH_A9M2440) := a9m2440 board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek diff -urN barebox-2011.06.0/drivers/mci/mci-core.c barebox-2011.06.0-vmx51/drivers/mci/mci-core.c --- barebox-2011.06.0/drivers/mci/mci-core.c 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/drivers/mci/mci-core.c 2011-06-10 13:48:29.782006230 +0200 @@ -1230,6 +1230,7 @@ p->read = mci_sd_read; p->priv = mci_dev; + disk_dev->id = -1; strcpy(disk_dev->name, "disk"); disk_dev->size = mci->capacity; disk_dev->map_base = 0; @@ -1370,6 +1371,7 @@ mci_dev = xzalloc(sizeof(struct device_d)); + mci_dev->id = -1; strcpy(mci_dev->name, mci_driver.name); mci_dev->platform_data = (void*)host; diff -urN barebox-2011.06.0/drivers/mfd/mc13892.c barebox-2011.06.0-vmx51/drivers/mfd/mc13892.c --- barebox-2011.06.0/drivers/mfd/mc13892.c 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/drivers/mfd/mc13892.c 2011-06-10 13:13:22.674514428 +0200 @@ -297,30 +297,35 @@ return 0; } +#ifdef CONFIG_I2C static int mc_i2c_probe(struct device_d *dev) { return mc_probe(dev, MC13892_MODE_I2C); } -static int mc_spi_probe(struct device_d *dev) -{ - return mc_probe(dev, MC13892_MODE_SPI); -} - static struct driver_d mc_i2c_driver = { .name = "mc13892-i2c", .probe = mc_i2c_probe, }; - +#endif +#ifdef CONFIG_SPI +static int mc_spi_probe(struct device_d *dev) +{ + return mc_probe(dev, MC13892_MODE_SPI); +} static struct driver_d mc_spi_driver = { .name = "mc13892-spi", .probe = mc_spi_probe, }; - +#endif static int mc_init(void) { +#ifdef CONFIG_I2C register_driver(&mc_i2c_driver); +#endif +#ifdef CONFIG_SPI register_driver(&mc_spi_driver); +#endif return 0; } diff -urN barebox-2011.06.0/Makefile barebox-2011.06.0-vmx51/Makefile --- barebox-2011.06.0/Makefile 2011-06-06 11:27:50.000000000 +0200 +++ barebox-2011.06.0-vmx51/Makefile 2011-06-10 13:13:22.674514428 +0200 @@ -163,8 +163,10 @@ # Alternatively CROSS_COMPILE can be set in the environment. # Default value for CROSS_COMPILE is not to prefix executables -ARCH ?= sandbox -CROSS_COMPILE ?= +#ARCH ?= sandbox +#CROSS_COMPILE ?= +ARCH ?= arm +CROSS_COMPILE ?= arm-none-linux-gnueabi- # Architecture as present in compile.h UTS_MACHINE := $(ARCH)