diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/board.c barebox-2012.09.0.work/arch/arm/boards/vmx25/board.c --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/board.c 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/board.c 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,472 @@ +/* + * (C) 2009 Pengutronix, Sascha Hauer + * (c) 2010 Eukrea Electromatique, Eric Bénard + * (c) 2010 Voipac Technologies + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __naked __flash_header_start go(void) +{ + barebox_arm_head(); +} + +struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x00095728, }, /* config */ + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92116480, }, /* control | precharge */ + { .ptr_type = 1, .addr = 0x80000400, .val = 0x12344321, }, /* command encoded in address */ + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2116480, }, /* auto refresh */ + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, /* read dram twice to auto refresh */ + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2116480, }, /* control | load mode */ + { .ptr_type = 1, .addr = 0x80000033, .val = 0x12344321, }, /* command encoded in address */ + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82116480, }, /* control | normal (0)*/ + { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, +}; + +struct imx_flash_header __flash_header_section vmx25_header = { + .app_code_jump_vector = DEST_BASE + 0x2000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = FLASH_HEADER_BASE/*TEXT_BASE + 0x400*/ + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = FLASH_HEADER_BASE/*TEXT_BASE + 0x400*/ + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = DEST_BASE, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof(dcd_entry), +}; + +unsigned long __image_len_section barebox_len = 0x40000; + +static struct fec_platform_data fec_info = { + .xcv_type = RMII, + .phy_addr = 0x1f, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +#ifdef CONFIG_DRIVER_VIDEO_IMX + +#define VMX25_PSAVE IMX_GPIO_NR(4, 3) + +static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 30076, + .hsync_len = 64, + .left_margin = 96, + .right_margin = 48, + .vsync_len = 2, + .upper_margin = 33, + .lower_margin = 10, + }, + .pcr = 0xFAC00080, + .bpp = 16, +}; + +static struct imx_fb_platform_data vmx25_fb_data = { + .mode = &imxfb_mode, + .num_modes = 1, + .pwmr = 0x0, + .lscr1 = 0x0, + .dmacr = 0x80040060, +}; +#endif + +#ifdef CONFIG_LED_GPIO + +#define VMX25_LGPIO0 IMX_GPIO_NR(2, 4) +#define VMX25_LGPIO1 IMX_GPIO_NR(2, 5) + +// LGPIO0 = GPIO2_4 +static struct gpio_led led0red = { + .led.name = "red", + .gpio = VMX25_LGPIO0, + .active_low = 0, +}; + +// LGPIO1 = GPIO2_5 +static struct gpio_led led1orange = { + .led.name = "orange", + .gpio = VMX25_LGPIO1, + .active_low = 0, +}; +#endif + +#ifdef CONFIG_USB +static void imx25_usb_init(void) +{ + unsigned int tmp; + + /* Host 1 */ + tmp = readl(IMX_OTG_BASE + 0x600); + tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; + tmp |= MX35_H1_USBTE_BIT; + tmp |= MX35_H1_IPPUE_DOWN_BIT; + writel(tmp, IMX_OTG_BASE + 0x600); + + tmp = readl(IMX_OTG_BASE + 0x584); + tmp |= 3 << 30; + writel(tmp, IMX_OTG_BASE + 0x584); + + /* Set to Host mode */ + tmp = readl(IMX_OTG_BASE + 0x5a8); + writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); +} +#endif + +#ifdef CONFIG_USB_GADGET_DRIVER_ARC +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, +// .operating_mode = FSL_USB2_DR_HOST, + .phy_mode = FSL_USB2_PHY_UTMI, +}; +#endif + +#ifdef CONFIG_DRIVER_SPI_IMX + +#define VMX25_CSPI1_CS0 IMX_GPIO_NR(1, 16) // GPIO1_16 +#define VMX25_CSPI1_CS1 IMX_GPIO_NR(1, 17) // GPIO1_17 + +static int spi_0_cs[] = { VMX25_CSPI1_CS0 , VMX25_CSPI1_CS1 }; + +static struct spi_imx_master spi_0_data = { + .chipselect = spi_0_cs, + .num_chipselect = ARRAY_SIZE(spi_0_cs), +}; + +static const struct spi_board_info mx25_spi_board_info[] = { + { + .name = "m25p", + .max_speed_hz = 300000, + .bus_num = 0, + .chip_select = 0, + }, + { + .name = "m25p", + .max_speed_hz = 300000, + .bus_num = 0, + .chip_select = 1, + }, +}; +#endif + +static iomux_v3_cfg_t vmx25_pads[] = { + /* UART1 */ + MX25_PAD_UART1_TXD__UART1_TXD, + MX25_PAD_UART1_RXD__UART1_RXD, + MX25_PAD_UART1_CTS__UART1_CTS, + MX25_PAD_UART1_RTS__UART1_RTS, + /* FEC */ + MX25_PAD_D11__GPIO_4_9, // FEC_PEN + MX25_PAD_D13__GPIO_4_7, // FEC_RESET_B + MX25_PAD_FEC_MDC__FEC_MDC, + MX25_PAD_FEC_MDIO__FEC_MDIO, + MX25_PAD_FEC_TDATA0__FEC_TDATA0, + MX25_PAD_FEC_TDATA1__FEC_TDATA1, + MX25_PAD_FEC_TX_EN__FEC_TX_EN, + MX25_PAD_FEC_RDATA0__FEC_RDATA0, + MX25_PAD_FEC_RDATA1__FEC_RDATA1, + MX25_PAD_FEC_RX_DV__FEC_RX_DV, + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX25_PAD_FEC_TX_EN__FEC_TX_EN, +#ifdef CONFIG_DRIVER_VIDEO_IMX + /* LCDC */ + MX25_PAD_LD0__LD0, + MX25_PAD_LD1__LD1, + MX25_PAD_LD2__LD2, + MX25_PAD_LD3__LD3, + MX25_PAD_LD4__LD4, + MX25_PAD_LD5__LD5, + MX25_PAD_LD6__LD6, + MX25_PAD_LD7__LD7, + MX25_PAD_LD8__LD8, + MX25_PAD_LD9__LD9, + MX25_PAD_LD10__LD10, + MX25_PAD_LD11__LD11, + MX25_PAD_LD12__LD12, + MX25_PAD_LD13__LD13, + MX25_PAD_LD14__LD14, + MX25_PAD_LD15__LD15, + MX25_PAD_GPIO_E__LD16, + MX25_PAD_GPIO_F__LD17, + MX25_PAD_LSCLK__LSCLK, + MX25_PAD_OE_ACD__OE_ACD, + MX25_PAD_VSYNC__VSYNC, + MX25_PAD_HSYNC__HSYNC, + // BACKLIGHT CONTROL + MX25_PAD_PWM__GPIO_1_26, + // PSAVE + MX25_PAD_CS1__GPIO_4_3, +#endif +#ifdef CONFIG_LED_GPIO + MX25_PAD_A18__GPIO_2_4, // LGPIO0 + MX25_PAD_A19__GPIO_2_5, // LGPIO1 +#endif +#ifdef CONFIG_USB + /* USB */ + MX25_PAD_D9__GPIO_4_11, // USBH1_PEN + MX25_PAD_GPIO_A__GPIO_A, // USBO_PEN +#endif +#ifdef CONFIG_I2C_IMX + /* I2C */ +// MX25_PAD_I2C1_CLK__SCL, +// MX25_PAD_I2C1_DAT__SDA, + MX25_PAD_I2C1_CLK__I2C1_CLK, + MX25_PAD_I2C1_DAT__I2C1_DAT, +#endif +#ifdef CONFIG_DRIVER_SPI_IMX + MX25_PAD_CSPI1_MOSI__CSPI1_MOSI, + MX25_PAD_CSPI1_MISO__CSPI1_MISO, + MX25_PAD_CSPI1_SS0__GPIO_1_16, + MX25_PAD_CSPI1_SS1__GPIO_1_17, + MX25_PAD_CSPI1_SCLK__CSPI1_SCLK, + MX25_PAD_CSPI1_RDY__CSPI1_RDY, +#endif +#ifdef CONFIG_MCI_IMX_ESDHC + /* SDCARD */ + MX25_PAD_SD1_CLK__SD1_CLK, + MX25_PAD_SD1_CMD__SD1_CMD, + MX25_PAD_SD1_DATA0__SD1_DATA0, + MX25_PAD_SD1_DATA1__SD1_DATA1, + MX25_PAD_SD1_DATA2__SD1_DATA2, + MX25_PAD_SD1_DATA3__SD1_DATA3, + MX25_PAD_D10__GPIO_4_10, // SD1_SEL +#endif + /* RESET OUT */ + MX25_PAD_VSTBY_ACK__GPIO_3_18, /* GPIO3_18 */ +}; + +#define VMX25_FEC_RESET IMX_GPIO_NR(4, 7) +#define VMX25_FEC_PEN IMX_GPIO_NR(4, 9) + +static void vmx25_fec_init(void) +{ + static iomux_v3_cfg_t fec_gpio_pads[] = { + MX25_PAD_D11__GPIO_4_9, // FEC_PEN + MX25_PAD_D13__GPIO_4_7, // FEC_RESET_B + MX25_PAD_FEC_RDATA0__GPIO_3_10, + MX25_PAD_FEC_RDATA1__GPIO_3_11, + MX25_PAD_FEC_RX_DV__GPIO_3_12, + }; + + mxc_iomux_v3_setup_multiple_pads(fec_gpio_pads, + ARRAY_SIZE(fec_gpio_pads)); + + // assert PHY reset, turn off PHY power + gpio_direction_output(VMX25_FEC_RESET, 0); // GPIO4_7 + gpio_direction_output(VMX25_FEC_PEN, 0); // GPIO4_9 + + mdelay(5); + + // turn on PHY power + gpio_direction_output(VMX25_FEC_PEN, 1); // GPIO4_9 + + mdelay(10); + + // set PHY mode pins to 1 + gpio_direction_output(IMX_GPIO_NR(3, 10), 1); // GPIO3_10 + gpio_direction_output(IMX_GPIO_NR(3, 11), 1); // GPIO3_11 + gpio_direction_output(IMX_GPIO_NR(3, 12), 1); // GPIO3_12 + + mdelay(22); + + // deassert PHY reset + gpio_set_value(VMX25_FEC_RESET, 1); // GPIO4_7 + + mdelay(5); +} + +static int vmx25_sdram_init(void) +{ + uchar rows, cols; + uint32_t size, esdctl; + + esdctl = readl(IMX_ESD_BASE); + rows = ((esdctl >> 24) & 7); + cols = ((esdctl >> 20) & 3); + size = (esdctl)? 1 << (rows + cols + 22) : 0; + + printk("SDRAM at 0x%08x: %dMB (%dMb, %d ROWs, %d COLs)\n", + IMX_SDRAM_CS0, size >> 20, size >> 17, rows + 11, cols + 8); + + arm_add_mem_device("ram0", IMX_SDRAM_CS0, size); + + esdctl = readl(IMX_ESD_BASE + 0x08); + rows = ((esdctl >> 24) & 7); + cols = ((esdctl >> 20) & 3); + size = (esdctl)? 1 << (rows + cols + 22) : 0; + + printk("SDRAM at 0x%08x: %dMB (%dMb, %d ROWs, %d COLs)\n", + IMX_SDRAM_CS1, size >> 20, size >> 17, rows + 11, cols + 8); + + arm_add_mem_device("ram0", IMX_SDRAM_CS1, size); + + add_mem_device("ram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE); + + return 0; +} + +mem_initcall(vmx25_sdram_init); + +#define VMX25_RESET_OUT IMX_GPIO_NR(3, 18) + +#define VMX25_SD1_SEL IMX_GPIO_NR(4, 10) + +static int vmx25_devices_init(void) +{ + /* assert RESET_OUT_B */ + gpio_direction_output(VMX25_RESET_OUT, 0); // GPIO3_18 + + vmx25_fec_init(); + + mxc_iomux_v3_setup_multiple_pads(vmx25_pads, + ARRAY_SIZE(vmx25_pads)); + +#ifdef CONFIG_LED_GPIO + gpio_direction_output( VMX25_LGPIO0, 0); + gpio_direction_output( VMX25_LGPIO1, 1); + + led_gpio_register(&led0red); + led_gpio_register(&led1orange); +#endif + + imx25_iim_register_fec_ethaddr(); + imx25_add_fec(&fec_info); + + imx25_add_nand(&nand_info); + + devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + // SRAM + arm_add_mem_device("sram0", 0x78000000, 128*1024); + +#ifdef CONFIG_DRIVER_VIDEO_IMX + // PSAVE + gpio_direction_output(VMX25_PSAVE, 1); // GPIO4_3 + imx25_add_fb(&vmx25_fb_data); +#endif +#ifdef CONFIG_I2C_IMX + imx25_add_i2c0(NULL); +#endif +#ifdef CONFIG_DRIVER_SPI_IMX + gpio_direction_output(VMX25_CSPI1_CS0,1); + gpio_direction_output(VMX25_CSPI1_CS1,1); + + spi_register_board_info(mx25_spi_board_info, + ARRAY_SIZE(mx25_spi_board_info)); + imx25_add_spi0(&spi_0_data); +#endif +#ifdef CONFIG_MCI_IMX_ESDHC + gpio_direction_output(VMX25_SD1_SEL, 0); + imx25_add_mmc0(NULL); +#endif + +#ifdef CONFIG_USB + imx25_usb_init(); + add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL); +#endif +#ifdef CONFIG_USB_GADGET_DRIVER_ARC + /* Workaround ENGcm09152 */ + writel(readl(IMX_OTG_BASE + 0x608) | (1 << 23), IMX_OTG_BASE + 0x608); + add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200, + IORESOURCE_MEM, &usb_pdata); +#endif + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_VMX25); + + gpio_direction_output(VMX25_RESET_OUT, 1); // deassert RESET_OUT + + return 0; +} + +device_initcall(vmx25_devices_init); + +static int vmx25_console_init(void) +{ + imx25_add_uart0(); + return 0; +} + +console_initcall(vmx25_console_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif + +static int vmx25_core_setup(void) +{ + /* enable UART1, FEC, SDHC, USB & I2C clock */ + writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 6) | (1 << 23) + | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28), + IMX_CCM_BASE + CCM_CGCR0); + writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 23) | (1 << 15) + | (1 << 13), IMX_CCM_BASE + CCM_CGCR1); + writel(readl(IMX_CCM_BASE + CCM_CGCR2) | (1 << 14), + IMX_CCM_BASE + CCM_CGCR2); + return 0; + +} + +core_initcall(vmx25_core_setup); + diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/config.h barebox-2012.09.0.work/arch/arm/boards/vmx25/config.h --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/config.h 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/config.h 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,26 @@ +/* + * (c) 2010 Voipac Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX25_HCLK_FREQ 24000000 + +#endif + diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/bin/boot barebox-2012.09.0.work/arch/arm/boards/vmx25/env/bin/boot --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/bin/boot 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/env/bin/boot 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,65 @@ +#!/bin/sh + +. /env/config + +image=/dev/nand0.kernel.bb + +if [ x$1 = xjffS2 ]; then + root=jffs2 + kernel=nand +fi + +if [ x$1 = xubifs ]; then + root=ubifs + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net + image=$zimage +fi + +if [ $# = 2 ]; then + image=$2 +fi + +if [ x$ip = xdhcp ]; then + if [ x$root = xnet ]; then + bootargs="$bootargs ip=dhcp" + fi +else + if [ x$ip = xoff ]; then + bootargs="$bootargs ip=off" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +fi + +if [ x$root = xjffs2 ]; then + bootargs="$bootargs root=/dev/mtdblock$rootpartnum_nand rootfstype=jffs2" +fi + +if [ x$root = xubifs ]; then + bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum_nand rootfstype=ubifs" +fi + +if [ x$root = xnet ]; then + bootargs="$bootargs root=/dev/nfs" + if [ ! -z "$rootpath" ]; then + bootargs="$bootargs nfsroot=$eth0.serverip:$rootpath" + fi +fi + +bootargs="$bootargs mtdparts=mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $image zImage || exit 1 + bootz zImage +else + bootz $image +fi + diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/bin/debug barebox-2012.09.0.work/arch/arm/boards/vmx25/env/bin/debug --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/bin/debug 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/env/bin/debug 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,28 @@ +#!/bin/sh + +. /env/config + +if [ x$ip = xdhcp ]; then + dhcp +fi + +bbdev=barebox-dev.bin +image=$basedir/$bbdev + +if [ $# = 1 ]; then + image=$1 +fi + +ping $eth0.serverip + +if [ $? -ne 0 ] ; then + echo "server not found" + exit 1 +fi + +tftp $image $bbdev + +if [ -e $bbdev ]; then + memcpy -s $bbdev 0 0x80000000 + go 0x80000000 +fi diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/bin/init barebox-2012.09.0.work/arch/arm/boards/vmx25/env/bin/init --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/bin/init 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/env/bin/init 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,39 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # hush workaround + nand0_parts="/dev/nand0.*" + nand -a $nand0_parts +fi + +if [ -f /env/logo.bmp ]; then + bmp /env/logo.bmp +elif [ -f /env/logo.bmp.lzo ]; then + unlzo /env/logo.bmp.lzo /logo.bmp + bmp /logo.bmp +fi + +#if [ -z $eth0.ethaddr ]; then +# while [ -z $eth0.ethaddr ]; do +# readline "No MAC address set for eth0. Please enter the one found on your module: " eth0.ethaddr +# done +# echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +# saveenv +#fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + exit +fi + +boot + diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/bin/update barebox-2012.09.0.work/arch/arm/boards/vmx25/env/bin/update --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/bin/update 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/env/bin/update 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,63 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xbarebox ]; then + image=$barebox + part=/dev/nand0.barebox.bb +fi + +if [ x$1 = xkernel ]; then + image=$zimage + part=/dev/nand0.kernel.bb +fi + +if [ x$1 = xrootfs ]; then + image=$rootfs + part=/dev/nand0.rootfs +fi + +if [ -z "$part" -o -z "$image" ]; then + echo "update barebox|kernel|rootfs []" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 2 ]; then + image=$2 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +if [ x$1 = xrootfs ]; then + echo + echo "attaching UBI to $part" + ubiattach $part + ubimkvol /dev/ubi0 rootfs 0 + + part=/dev/ubi0.rootfs +fi + +echo +echo "flashing $image to $part" +echo +tftp $image $part + diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/config barebox-2012.09.0.work/arch/arm/boards/vmx25/env/config --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/env/config 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/env/config 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,32 @@ +#!/bin/sh + +# can be either 'net' or 'jffs2' or 'ubifs' +kernel=nand +root=ubifs + +basedir=vmx25 +barebox=$basedir/barebox.bin +zimage=$basedir/zImage +rootfs=$basedir/rootfs.bin + +autoboot_timeout=3 + +# vmx25 modes +# video=imxfb:[VGA-LCD|VGA-16@60|VGA-32@60|WVGA-LCD|WVGA-16@60|WVGA-32@60|SVGA-16@60|SVGA-32@60] +bootargs="console=ttymxc0,115200 otg_mode=host video=imxfb:VGA-16@60" + +nand_parts="256k(barebox)ro,128k(bareboxenv),2688k(kernel),-(rootfs)" +spi_parts="256k(barebox)ro,128k(bareboxenv),-(kernel)" +rootpartnum_nand=3 +ubiroot="rootfs" + +# ip=off|static|dhcp +# use 'dhcp' to do dhcp in barebox and in kernel +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d +#eth0.ethaddr=00:01:02:03:04:05 diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/lowlevel_init.S barebox-2012.09.0.work/arch/arm/boards/vmx25/lowlevel_init.S --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/lowlevel_init.S 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/lowlevel_init.S 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,275 @@ +/* + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby + * + * Based on U-Boot and RedBoot sources for several different i.mx + * platforms. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* #include */ +.macro write32, addr, data + ldr r4, =\addr + ldr r5, =\data + str r5, [r4] +.endm + +.section ".text_bare_init","ax" + +init_aips: + write32 0x43f00000, 0x77777777 + write32 0x43f00004, 0x77777777 + write32 0x53f00000, 0x77777777 + write32 0x53f00004, 0x77777777 + mov pc, lr + +init_max: + write32 0x43f04000, 0x02143 + write32 0x43f04100, 0x02143 + write32 0x43f04200, 0x02143 + write32 0x43f04300, 0x02143 + write32 0x43f04400, 0x02143 + + write32 0x43f04010, 0x10 + write32 0x43f04110, 0x10 + write32 0x43f04210, 0x10 + write32 0x43f04310, 0x10 + write32 0x43f04410, 0x10 + + write32 0x43f04800, 0x0 + write32 0x43f04900, 0x0 + write32 0x43f04a00, 0x0 + write32 0x43f04b00, 0x0 + write32 0x43f04c00, 0x0 + mov pc, lr + +init_clocks: + /* + * clocks + * + * first enable CLKO debug output + * 0x40000000 enables the debug CLKO signal + * 0x05000000 sets CLKO divider to 6 + * 0x00600000 makes CLKO parent clk the USB clk + */ + write32 0x53f80064, 0x45600000 + write32 0x53f80008, 0x20034000 + + /* + * enable all implemented clocks in all three + * clock control registers + */ + write32 0x53f8000c, 0x1fffffff + write32 0x53f80010, 0xffffffff + write32 0x53f80014, 0xfdfff + mov pc, lr + +.macro init_ddrtype + /* + * ddr_type is 3.3v SDRAM + */ + write32 0x43fac454, 0x800 +.endm + +/* + * reset SDRAM controller + * then wait for initialization to complete + * r3 = 0xb8001000 + */ +reset_sdram_ctrl: + ldr r1, =(1 << 1) + str r1, [r3, #0x10] +1: ldr r0, [r3, #0x10] + tst r0, #(1 << 31) + beq 1b + mov pc, lr + +/* + * sdram controller init + * 13 ROWs, 10 COLs + * r2 = bank mem base + * r3 = bank regs base + */ +init_sdram_bank: + ldr r1, =0x95728 + str r1, [r3, #0x04] /* config */ + + ldr r1, =0x92216480 /* control | precharge */ + str r1, [r3] /* write command to controller */ + strb r1, [r2, #0x400] /* command encoded in address */ + + ldr r1, =0xa2216480 /* auto refresh */ + str r1, [r3] + ldrb r0, [r2] /* read dram twice to auto refresh */ + ldrb r0, [r2] + + ldr r1, =0xb2216480 /* control | load mode */ + str r1, [r3] /* write command to controller */ + strb r1, [r2, #0x33] /* command encoded in address */ + + ldr r1, =0x82216480 /* control | normal (0)*/ + str r1, [r3] /* write command to controller */ + + mov r0, #0 /* detect sdram bank presence pass1: r0=0 */ + str r0, [r2] + ldr r1, [r2] + cmp r0, r1 /* compare, set flags */ + bne bank_disable + + ldr r0, =0xdeadbeef /* detect sdram presence pass2: r0=0xdeadbeef */ + str r0, [r2] + ldr r1, [r2] + cmp r0, r1 /* compare, set flags */ + moveq pc, lr /* return if equal */ + +bank_disable: /* disable sdram bank */ + mov r0, #0 + str r0, [r3] + str r0, [r3, #0x04 ] + mov pc, lr + +set_columns: + mov r0, r2 /* r0 = 80000000 */ + +/* 8cols: 0x80000000 = 0x80000200 = 0x80000400 = 0x80000600 */ +/* 9cols: 0x80000000 = 0x80000400 */ +/* 10cols: 0x80000000 */ + + str r0, [r0], #0x400 /* [80000000] = 0 */ + str r0, [r0], #0x200 /* [80000400] = 80000400 */ + str r0, [r0] /* [80000600] = 80000600 */ + + ldrh r0, [r2] + movs r0, r0, LSL #0x0B + addeq r0, #0x100000 + eor r0, #0x300000 + and r0, #0x300000 /* r0 = #cols */ + + ldr r1, [r3] /* set cols */ + bic r1, #0x300000 + orr r1, r0 + str r1, [r3] + mov pc, lr + +set_rows: + mov r0, r2 /* r0 = 80000000 */ + mov r1, #0x400000 + +/* 13rows (32M16): 0x80000000 = 0x84000000 */ +/* 13rows (16M16): 0x80000000 = 0x82000000 = 0x84000000 */ +/* 12rows (8M16): 0x80000000 = 0x80400000 */ +/* 12rows (4M16): 0x80000000 = 0x80100000 = 0x80200000 = 0x80300000 = 0x80400000 */ + + str r0, [r0], r1 /* [80000000] = 0 */ + str r0, [r0], r1 /* [80400000] = 80400000 */ + + ldr r0, [r2] + mov r0, r0, LSL #0x2 + ands r0, #0x1000000 + addeq r0, #0x2000000 + and r0, #0x7000000 /* r0 = #rows */ + + ldr r1, [r3] /* set rows */ + bic r1, #0x7000000 + orr r1, r0 + str r1, [r3] + mov pc, lr + +.globl arch_init_lowlevel +arch_init_lowlevel: + mov r10, lr + + bl init_aips + bl init_max + + write32 0xb8003000, 0x1 /* init_m3if */ + + bl init_clocks + + /* init_sdram_bank 0x80000000, 0x0, 0x4 */ + ldr r2, =0x80000000 + + /* check not running from SDRAM */ + add r0, pc, #0x80000000 + cmp r0, #0x20000000 + + bls skip_sdram_init + + ldr r3, =0xb8001000 + + bl reset_sdram_ctrl + bl init_sdram_bank + + bne bank0_disabled + + bl set_columns + bl set_rows + +bank0_disabled: + /* init_sdram_bank 0x90000000, 0x8, 0xc */ + ldr r2, =0x90000000 + ldr r3, =0xb8001008 + + bl init_sdram_bank + + bne bank1_disabled + + bl set_columns + bl set_rows + +bank1_disabled: +skip_sdram_init: + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, STACK_BASE_W /* Setup a temporary stack */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + bls ret + cmp pc, r2 + bhi ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC SRAM */ + /* to SDRAM */ + +#endif /* CONFIG_NAND_IMX_BOOT */ +ret: + mov pc, r10 + +STACK_BASE_W: .word (STACK_BASE + STACK_SIZE -12) + diff -urN barebox-2012.09.0.orig/arch/arm/boards/vmx25/Makefile barebox-2012.09.0.work/arch/arm/boards/vmx25/Makefile --- barebox-2012.09.0.orig/arch/arm/boards/vmx25/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/boards/vmx25/Makefile 2015-11-23 20:54:50.547776333 +0100 @@ -0,0 +1,24 @@ +# +# (c) 2010 Voipac Technologies +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel_init.o +obj-y += board.o diff -urN barebox-2012.09.0.orig/arch/arm/configs/vmx25_defconfig barebox-2012.09.0.work/arch/arm/configs/vmx25_defconfig --- barebox-2012.09.0.orig/arch/arm/configs/vmx25_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ barebox-2012.09.0.work/arch/arm/configs/vmx25_defconfig 2015-11-23 20:54:50.551776333 +0100 @@ -0,0 +1,393 @@ +# +# Automatically generated file; DO NOT EDIT. +# Barebox/arm 2012.09.0 Configuration +# +CONFIG_ARM=y +CONFIG_ARM_LINUX=y + +# +# System Type +# +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_EP93XX is not set +CONFIG_ARCH_IMX=y +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_S3C24xx is not set +# CONFIG_ARCH_S3C64xx is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_TEGRA is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y + +# +# processor features +# +# CONFIG_BOOT_ENDIANNESS_SWITCH is not set +CONFIG_ARCH_TEXT_BASE=0x81f00000 +CONFIG_BOARDINFO="Voipac VMX25" +# CONFIG_ARCH_IMX_INTERNAL_BOOT is not set +CONFIG_ARCH_IMX_EXTERNAL_BOOT=y +CONFIG_NAND_IMX_BOOT=y +CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y +# CONFIG_NAND_IMX_BOOT_512 is not set +CONFIG_NAND_IMX_BOOT_2K=y +# CONFIG_NAND_IMX_BOOT_512_2K is not set + +# +# Freescale i.MX System-on-Chip +# +# CONFIG_ARCH_IMX1 is not set +# CONFIG_ARCH_IMX21 is not set +CONFIG_ARCH_IMX25=y +# CONFIG_ARCH_IMX27 is not set +# CONFIG_ARCH_IMX31 is not set +# CONFIG_ARCH_IMX35 is not set +# CONFIG_ARCH_IMX51 is not set +# CONFIG_ARCH_IMX53 is not set +# CONFIG_ARCH_IMX6 is not set +# CONFIG_MACH_EUKREA_CPUIMX25 is not set +# CONFIG_MACH_FREESCALE_MX25_3STACK is not set +CONFIG_MACH_VMX25=y +# CONFIG_MACH_TX25 is not set + +# +# Board specific settings +# + +# +# i.MX specific settings +# +# CONFIG_IMX_CLKO is not set +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_AEABI=y + +# +# Arm specific settings +# +CONFIG_CMD_ARM_CPUINFO=y +# CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS is not set +CONFIG_ARM_EXCEPTIONS=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG" +CONFIG_HAS_KALLSYMS=y +CONFIG_HAS_MODULES=y +CONFIG_CMD_MEMORY=y +CONFIG_ENV_HANDLING=y +CONFIG_GENERIC_GPIO=y +CONFIG_FILETYPE=y +CONFIG_BINFMT=y +CONFIG_STDDEV=y + +# +# General Settings +# +CONFIG_LOCALVERSION="-vmx25-vpac3" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BANNER=y +CONFIG_ENVIRONMENT_VARIABLES=y + +# +# memory layout +# +# CONFIG_MMU is not set +CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y +CONFIG_TEXT_BASE=0x81f00000 +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xffffffff +CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0xffffffff +CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y +CONFIG_MEMORY_LAYOUT_DEFAULT=y +# CONFIG_MEMORY_LAYOUT_FIXED is not set +CONFIG_STACK_SIZE=0x8000 +CONFIG_MALLOC_SIZE=0x800000 +# CONFIG_BROKEN is not set +# CONFIG_EXPERIMENTAL is not set +CONFIG_MALLOC_DLMALLOC=y +# CONFIG_MALLOC_TLSF is not set +# CONFIG_KALLSYMS is not set +CONFIG_ARCH_HAS_LOWLEVEL_INIT=y +CONFIG_PROMPT="barebox:" +CONFIG_BAUDRATE=115200 +CONFIG_LONGHELP=y +CONFIG_CBSIZE=1024 +CONFIG_MAXARGS=16 +CONFIG_SHELL_HUSH=y +# CONFIG_SHELL_SIMPLE is not set +CONFIG_GLOB=y +# CONFIG_GLOB_SORT is not set +CONFIG_PROMPT_HUSH_PS2="> " +# CONFIG_HUSH_FANCY_PROMPT is not set +# CONFIG_HUSH_GETOPT is not set +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_PASSWORD is not set +CONFIG_DYNAMIC_CRC_TABLE=y +CONFIG_ERRNO_MESSAGES=y +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_FULL=y +CONFIG_CONSOLE_ACTIVATE_FIRST=y +CONFIG_PARTITION=y +CONFIG_PARTITION_DISK=y +CONFIG_PARTITION_DISK_DOS=y +CONFIG_DEFAULT_ENVIRONMENT=y +CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED=y +CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_GZIP=y +# CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW is not set +# CONFIG_DEFAULT_ENVIRONMENT_GENERIC is not set +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/vmx25/env" +# CONFIG_BAREBOXENV_TARGET is not set +CONFIG_POLLER=y + +# +# Debugging +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_FLASH_NOISE is not set +# CONFIG_ENABLE_PARTITION_NOISE is not set +# CONFIG_ENABLE_DEVICE_NOISE is not set +CONFIG_COMMAND_SUPPORT=y +# CONFIG_HAS_POWEROFF is not set + +# +# commands +# + +# +# scripting +# +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +# CONFIG_CMD_MSLEEP is not set +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TRUE=y +CONFIG_CMD_FALSE=y +# CONFIG_CMD_LOGIN is not set +# CONFIG_CMD_PASSWD is not set +# CONFIG_CMD_TIME is not set +# CONFIG_CMD_GLOBAL is not set + +# +# file commands +# +CONFIG_CMD_LS=y +CONFIG_CMD_RM=y +CONFIG_CMD_CAT=y +CONFIG_CMD_MKDIR=y +CONFIG_CMD_RMDIR=y +CONFIG_CMD_CP=y +CONFIG_CMD_PWD=y +CONFIG_CMD_CD=y +CONFIG_CMD_MOUNT=y +CONFIG_CMD_UMOUNT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NANDTEST=y +# CONFIG_CMD_AUTOMOUNT is not set +# CONFIG_CMD_BASENAME is not set +# CONFIG_CMD_DIRNAME is not set + +# +# console +# +CONFIG_CMD_CLEAR=y +CONFIG_CMD_ECHO=y +# CONFIG_CMD_ECHO_E is not set + +# +# memory +# +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADY is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +# CONFIG_CMD_CRC is not set +CONFIG_CMD_DIGEST=y +CONFIG_CMD_MD5SUM=y +# CONFIG_CMD_SHA1SUM is not set +# CONFIG_CMD_SHA256SUM is not set +# CONFIG_CMD_SHA224SUM is not set +CONFIG_CMD_MTEST=y +# CONFIG_CMD_MTEST_ALTERNATIVE is not set + +# +# flash +# +CONFIG_CMD_FLASH=y +CONFIG_CMD_UBI=y + +# +# booting +# +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_UIMAGE is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +# CONFIG_CMD_OFTREE is not set +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_TEST=y +CONFIG_CMD_VERSION=y +CONFIG_CMD_HELP=y +CONFIG_CMD_MAGICVAR=y +# CONFIG_CMD_MAGICVAR_HELP is not set +CONFIG_CMD_DEVINFO=y +# CONFIG_CMD_BMP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +# CONFIG_NET_NFS is not set +CONFIG_NET_PING=y +CONFIG_NET_TFTP=y +CONFIG_NET_TFTP_PUSH=y +CONFIG_NET_NETCONSOLE=y +# CONFIG_NET_RESOLV is not set + +# +# Drivers +# + +# +# serial drivers +# +# CONFIG_DRIVER_SERIAL_ARM_DCC is not set +CONFIG_DRIVER_SERIAL_IMX=y +# CONFIG_DRIVER_SERIAL_NS16550 is not set +CONFIG_ARCH_HAS_FEC_IMX=y +CONFIG_MIIDEV=y + +# +# Network drivers +# +# CONFIG_DRIVER_NET_SMC911X is not set +# CONFIG_DRIVER_NET_SMC91111 is not set +CONFIG_DRIVER_NET_FEC_IMX=y +# CONFIG_DRIVER_NET_KS8851_MLL is not set + +# +# SPI drivers +# +CONFIG_SPI=y +CONFIG_DRIVER_SPI_IMX=y +CONFIG_DRIVER_SPI_IMX_0_7=y +CONFIG_I2C=y + +# +# I2C Hardware Bus support +# +CONFIG_I2C_IMX=y + +# +# flash drivers +# +# CONFIG_DRIVER_CFI is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +CONFIG_MTD=y +CONFIG_MTD_WRITE=y +CONFIG_MTD_OOB_DEVICE=y +# CONFIG_MTD_RAW_DEVICE is not set + +# +# Self contained MTD devices +# +# CONFIG_MTD_DOCG3 is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +CONFIG_NAND_ECC_HW=y +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_INFO=y +CONFIG_NAND_READ_OOB=y +CONFIG_NAND_BBT=y +CONFIG_NAND_IMX=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_UBI=y +# CONFIG_DISK is not set +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set +CONFIG_USB_HAVE_GADGET_DRIVER=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_IMX=y +# CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY is not set +# CONFIG_MCI is not set + +# +# MFD +# +# CONFIG_MFD_MC13XXX is not set +# CONFIG_I2C_MC34704 is not set +# CONFIG_I2C_MC34708 is not set +# CONFIG_I2C_MC9SDZ60 is not set +# CONFIG_I2C_LP3972 is not set +# CONFIG_I2C_TWL4030 is not set +# CONFIG_I2C_TWL6030 is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y +# CONFIG_LED_GPIO_RGB is not set +CONFIG_LED_TRIGGERS=y + +# +# EEPROM support +# +# CONFIG_EEPROM_AT25 is not set + +# +# Input device support +# +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_IMX_KEYPAD is not set +# CONFIG_WATCHDOG is not set +# CONFIG_PWM is not set + +# +# DMA support +# + +# +# Filesystem support +# +# CONFIG_FS_CRAMFS is not set +CONFIG_FS_RAMFS=y +CONFIG_FS_DEVFS=y +# CONFIG_FS_TFTP is not set +# CONFIG_FS_NFS is not set +# CONFIG_FS_FAT is not set +CONFIG_PARTITION_NEED_MTD=y + +# +# Library routines +# +CONFIG_PARAMETER=y +CONFIG_UNCOMPRESS=y +CONFIG_ZLIB=y +# CONFIG_BZLIB is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +# CONFIG_PROCESS_ESCAPE_SEQUENCE is not set +# CONFIG_LZO_DECOMPRESS is not set +CONFIG_CRC32=y +CONFIG_DIGEST=y +CONFIG_MD5=y +# CONFIG_SHA1 is not set +# CONFIG_SHA224 is not set +# CONFIG_SHA256 is not set diff -urN barebox-2012.09.0.orig/arch/arm/mach-imx/Kconfig barebox-2012.09.0.work/arch/arm/mach-imx/Kconfig --- barebox-2012.09.0.orig/arch/arm/mach-imx/Kconfig 2012-09-05 12:57:01.000000000 +0200 +++ barebox-2012.09.0.work/arch/arm/mach-imx/Kconfig 2015-11-23 20:54:50.551776333 +0100 @@ -17,6 +17,7 @@ default 0x87f00000 if MACH_PCM043 default 0x08f80000 if MACH_SCB9328 default 0xa7e00000 if MACH_NESO + default 0x81f00000 if MACH_VMX25 default 0x97f00000 if MACH_MX51_PDK default 0x7ff00000 if MACH_MX53_LOCO default 0x7ff00000 if MACH_MX53_SMD @@ -43,6 +44,7 @@ default "Phytec phyCORE-i.MX35" if MACH_PCM043 default "Synertronixx scb9328" if MACH_SCB9328 default "Garz+Fricke Neso" if MACH_NESO + default "Voipac VMX25" if MACH_VMX25 default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK default "Freescale i.MX53 LOCO" if MACH_FREESCALE_MX53_LOCO default "Freescale i.MX53 SMD" if MACH_FREESCALE_MX53_SMD @@ -253,6 +255,13 @@ Say Y here if you are using the Freescale MX25 3stack board equipped with a Freescale i.MX25 Processor +config MACH_VMX25 + bool "Voipac VMX25" + select ARCH_HAS_LOWLEVEL_INIT + help + Say Y here if you are using the Voipac Technologies VMX25 module + equipped with a Freescale i.MX25 Processor + config MACH_TX25 bool "Ka-Ro TX25" select MACH_HAS_LOWLEVEL_INIT diff -urN barebox-2012.09.0.orig/arch/arm/Makefile barebox-2012.09.0.work/arch/arm/Makefile --- barebox-2012.09.0.orig/arch/arm/Makefile 2012-09-05 12:57:01.000000000 +0200 +++ barebox-2012.09.0.work/arch/arm/Makefile 2015-11-23 20:54:50.551776333 +0100 @@ -113,6 +113,7 @@ board-$(CONFIG_MACH_PM9G45) := pm9g45 board-$(CONFIG_MACH_SCB9328) := scb9328 board-$(CONFIG_MACH_NESO) := guf-neso +board-$(CONFIG_MACH_VMX25) := vmx25 board-$(CONFIG_MACH_MX23EVK) := freescale-mx23-evk board-$(CONFIG_MACH_CHUMBY) := chumby_falconwing board-$(CONFIG_MACH_TX28) := karo-tx28 diff -urN barebox-2012.09.0.orig/drivers/mtd/nand/nand_ids.c barebox-2012.09.0.work/drivers/mtd/nand/nand_ids.c --- barebox-2012.09.0.orig/drivers/mtd/nand/nand_ids.c 2012-09-05 12:57:01.000000000 +0200 +++ barebox-2012.09.0.work/drivers/mtd/nand/nand_ids.c 2015-11-23 20:54:50.551776333 +0100 @@ -91,6 +91,7 @@ /* 1 Gigabit */ {__NANDSTR("NAND 128MiB 1,8V 8-bit"), 0xA1, 0, 128, 0, LP_OPTIONS}, {__NANDSTR("NAND 128MiB 3,3V 8-bit"), 0xF1, 0, 128, 0, LP_OPTIONS}, + {__NANDSTR("NAND 128MiB 3,3V 8-bit"), 0xD1, 0, 128, 0, LP_OPTIONS}, {__NANDSTR("NAND 128MiB 1,8V 16-bit"), 0xB1, 0, 128, 0, LP_OPTIONS16}, {__NANDSTR("NAND 128MiB 3,3V 16-bit"), 0xC1, 0, 128, 0, LP_OPTIONS16}, @@ -118,6 +119,7 @@ {__NANDSTR("NAND 2GiB 1,8V 16-bit"), 0xB5, 0, 2048, 0, LP_OPTIONS16}, {__NANDSTR("NAND 2GiB 3,3V 16-bit"), 0xC5, 0, 2048, 0, LP_OPTIONS16}, + {__NANDSTR("NAND 2GiB 3,3V 8-bit"), 0x48, 0, 4096, 0, 0}, /* * Renesas AND 1 Gigabit. Those chips do not support extended id and * have a strange page/block layout ! The chosen minimum erasesize is diff -urN barebox-2012.09.0.orig/drivers/nor/m25p80.c barebox-2012.09.0.work/drivers/nor/m25p80.c --- barebox-2012.09.0.orig/drivers/nor/m25p80.c 2012-09-05 12:57:01.000000000 +0200 +++ barebox-2012.09.0.work/drivers/nor/m25p80.c 2015-11-23 20:56:28.199774404 +0100 @@ -600,6 +600,7 @@ { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) }, { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) }, { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) }, + { "sst26vf032b", INFO(0xbf2642, 0, 64 * 1024, 64, SECT_4K) }, /* ST Microelectronics -- newer production may have feature updates */ { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, diff -urN barebox-2012.09.0.orig/drivers/spi/spi.c barebox-2012.09.0.work/drivers/spi/spi.c --- barebox-2012.09.0.orig/drivers/spi/spi.c 2012-09-05 12:57:01.000000000 +0200 +++ barebox-2012.09.0.work/drivers/spi/spi.c 2015-11-23 20:54:50.551776333 +0100 @@ -81,6 +81,7 @@ /* allocate a free id for this chip */ proxy->dev.id = DEVICE_ID_DYNAMIC; proxy->dev.type_data = proxy; + proxy->dev.id=-1; dev_add_child(master->dev, &proxy->dev); /* drivers may modify this initial i/o setup */